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riva 128 ? 128-bit 3d multimedia accelerator ? ? 1/77 the information in this datasheet is subject to change 42 1687 01 (sgs-thomson) october 1997 block diagram palette dac yuv - rgb, graphics engine 128 bit 2d direct3d sgram interface vga dma bus internal bus ccir656 video pci/a gp 128 bit interface monitor/ tv 1.6 gbyte/s internal bus bandwidth dma engine video port x & y scaler host interface fifo/ dma pusher dma engine description the riva 128 ? is the first 128-bit 3d multimedia accelerator to offer unparalleled 2d and 3d perfor- mance, meeting all the requirements of the main- stream pc graphics market and microsoft's pc'97. the riva 128 introduces the most ad- vanced direct3d ? acceleration solution and also delivers leadership vga, 2d and video perfor- mance, enabling a range of applications from 3d games through to dvd, intercast ? and video con- ferencing. key features ? fast 32-bit vga/svga ? high performance 128-bit 2d/gui/directdraw acceleration ? interactive, photorealistic direct3d accelera- tion with advanced effects ? massive 1.6gbytes/s, 100mhz 128-bit wide frame buffer interface ? video acceleration for directdraw/directvideo, mpeg-1/2 and indeo ? - planar 4:2:0 and packed 4:2:2 color space conversion - x and y smooth up and down scaling ? 230mhz palette-dac supporting up to 1600x1200@75hz ? ntsc and pal output with flicker-filter ? multi-function video port and serial interface ? bus mastering dma 66mhz accelerated graphics port (agp) 1.0 interface ? bus mastering dma pci 2.1 interface ? 0.35 micron 5lm cmos ? 300 pbga
riva 128 128-bit 3d multimedia accelerator table of contents 2/77 1 revision history..................................................... ................................................ ................. 4 1 riva 128 300pbga device pinout......................... ................................................ ................. 5 2 pin descriptions ..................................................... ................................................ ................. 6 2.1 accelerated graphics port (agp) interface.................................... ................. 6 2.2 pci 2.1 local bus interface ............................................... ......................................... 6 2.3 sgram framebuffer interface ......................... ................................................ ....... 8 2.4 video port......................... ................................................ ................................................ 8 2.5 device enable signals.................................................. ................................................ 9 2.6 display interface ................. ................................................ ......................................... 9 2.7 video dac and pll analog signals ................................. ......................................... 9 2.8 power supply .......................................... ................................................ ........................ 9 2.9 test............................................. ................................................ ................................... ...... 10 3 overview of the riva 128............. ................................................ ......................................... 11 3.1 balanced pc system............. ................................................ ......................................... 11 3.2 host interface ...................... ................................................ ......................................... 11 3.3 2d acceleration ............................................ ......................................... ........................ 12 3.4 3d engine ............. ...................................... ................................................ ........................ 12 3.5 video processor..................................................... ................................................ ....... 12 3.6 video port......................... ................................................ ................................................ 13 3.7 direct rgb output to low cost pal/ntsc encoder.......... ............................... 13 3.8 support for standards....................................... ................................................ ....... 13 3.9 resolutions supported....................................... ................................................ ....... 13 3.10 customer evaluation kit............. ...................................... ......................................... 14 3.11 turnkey manufacturing package........................... ......................................... ....... 14 4 accelerated graphics port (agp) interface............. ................................................ 15 4.1 riva 128 agp interface ........................................................ ......................................... 16 4.2 agp bus transactions.................................................. ................................................ 16 5 pci 2.1 local bus interface........................................................ ......................................... 22 5.1 riva 128 pci interface .................................. ................................................ ................. 22 5.2 pci timing specification.............................. ......................................... ........................ 23 6 sgram framebuffer interface.................................. ................................................ ....... 29 6.1 sgram initialization ............. ................................................ ......................................... 31 6.2 sgram mode register .................................................. ................................................ 31 6.3 layout of framebuffer clock signals ................................. ............................... 32 6.4 sgram interface timing specification........... ................................................ ....... 32 7 video playback architecture................... ................................................ ........................ 37 7.1 video scaler pipeline.................................. ................................................ ................. 38 8 video port.................................. ................................................ .............................................. .. 40 8.1 video interface port features ............................... ................................................ 40 8.2 bi-directional media port polling commands using mpc ............. ................. 41 8.3 timing diagrams ............................... ................................................ ............................... 42 8.4 656 master mode ............................................ ......................................... ........................ 46 8.5 vbi handling in the video port ................ ................................................ ................. 47 8.6 scaling in the video port ................... ................................................ ........................ 47 9 boot rom interface...................... ................................................ ......................................... 48
128-bit 3d multimedia accelerator riva 128 3/77 10 power-on reset configuration............................................... ......................................... 50 11 display interface.................................... ................................................ ............................... 52 11.1 palette-dac ..................................................... ................................................ ................. 52 11.2 pixel modes supported.............................. ......................................... ........................ 52 11.3 hardware cursor ................................. ................................................ ........................ 53 11.4 i2c interface........................... ......................................... ................................................ 54 11.5 analog interface ................. ................................................ ......................................... 55 11.6 tv output support....................................... ................................................ ................. 56 12 in-circuit board testing............. ................................................ ......................................... 58 12.1 test modes ............................................... ......................................... ............................... 58 12.2 checksum test................ ................................................ ......................................... ....... 58 13 electrical specifications .................................................. ................................................ 59 13.1 absolute maximum ratings ............................................... ......................................... 59 13.2 operating conditions.................................................. ................................................ 59 13.3 dc specifications........... ................................................ ................................................ 59 13.4 electrical specifications......................... ................................................ ................. 60 13.5 dac characteristics ............................ ................................................ ........................ 60 13.6 frequency synthesis characteristics................................. ............................... 61 14 package dimension specification.................................... ................................................ 62 14.1 300 pin ball grid array package ............................................... ............................... 62 15 references........................................................ ................................................ ........................ 63 16 ordering information ................. ................................................ ......................................... 63 appendix............................................. ................................................ ................................... ...... 64 a pci configuration registers............................................. ................................................ 64 a.1 register descriptions for pci configuration space .................................... 64
128-bit 3d multimedia accelerator riva 128 4/77 1 revision history date section, page description of change 15 jul 97 6, page 28 update of sgram framebuffer interface configuration diagrams. 28 aug 97 13.5, page 59 change of dac specification from 206mhz to 230mhz max. operating frequency. 29 aug 97 6.3, page 31 update to recommendation for connection of fbclk2 and fbclkb pins. 4 sep 97 10, page 49 update to ram type power-on reset configuration bits. 15 sep 97 13, page 58 temperature specific ation tc now based on case, not ambient temperature. 15 sep 97 13, page 58 change to power supply voltage vdd specification. 17 sep 97 1, page 5 change to video port pin names. 17 sep 97 2, page 6 change to video port pin descriptions. 17 sep 97 8, page 39 updates to video port section. 18 sep 97 11.6, page 55 change to capacitor value in tv output implementation schematic. 18 sep 97 13.3, page 58 change to power dissipation specification . 25 sep 97 4.2, page 16 removal of agp flow control description. 25 sep 97 11.4, page 53 updates to serial port description.
128-bit 3d multimedia accelerator riva 128 5/77 1 riva 128 300pbga device pinout notes 1 nic = no internal conn ection. do not connect to these pins. 2 vdd=3.3v * signals deno ted with an asterisk are defined for future expansion. see pin descriptions , section 2, page 6 for details. 1234567891011121314151617181920 a fbd[4] fbd[6] fbd[7] fbd[17] fbd[19] fbd[21] fbd[23] fbdqm[2] fba[0] fba[2] fba[4] fba[6] fba[8] fbdqm[5] fbd[41] fbd[43] fbd[45] fbd[47] fbd[56] fbd[57] b fbd[3] fbd[5] fbd[16] fbd[18] fbd[20] fbd[22] fbdqm[0] fba[9] fba[1] fba[3] fba[5] fba[7] fbclk1 fbdqm[7] fbd[40] fbd[42] fbd[44] fbd[46] fbd[58] fbd[59] c fbd[1] fbd[2] fbd[28] fbd[27] fbd[26] fbd[25] fbd[15] fbd[13] fbd[11] fbd[9] fbdqm[1] fbwe# fbras# fba[10] * fbdqm[4] fbd[55] fbd[54] fbd[53] fbd[60] fbd[61] d fbclk0 fbd[0] fbd[29] fbd[30] vdd fbd[24] fbd[14] fbd[12] fbd[10] fbd[8] fbdqm[3] fbcas# fbcs0 fbcs1 fbdqm[6] vdd fbd[52] fbd[51] fbd[62] fbd[63] e scl fbclk2 fbd[31] vdd nic vdd vdd vdd fbcke * vdd vdd vdd vdd fbd[50] fbd[39] fbd[38] f mp_ad[6] nic sda fbclkfb vdd vdd fbd[48] fbd[49] fbd[37] fbd[36] g mpframe# mp_ad[7] mp_ad[5] mp_ad[4] mpclamp vdd fbd[35] fbd[34] fbd[33] fbd[32] h mp_ad[2] mpstop# mpclk mp_ad[3] vdd nic fbdqm[12] fbdqm[14] fbdqm[15] fbdqm[13] j fbdqm[8] mpdtack# mp_ad[1] mp_ad[0] gnd gnd gnd gnd fbd[118] fbd[119] fbd[105] fbd[104] k fbdqm[9] fbd[87] fbdqm[10] fbdqm[11] gnd gnd gnd gnd fbd[116] fbd[117] fbd[107] fbd[106] l fbd[86] fbd[85] fbd[72] fbd[73] gnd gnd gnd gnd fbd[114] fbd[115] fbd[109] fbd[108] m fbd[84] fbd[83] fbd[74] fbd[75] gnd gnd gnd gnd fbd[112] fbd[113] fbd[111] fbd[110] n fbd[82] fbd[81] fbd[76] fbd[77] nic nic fbd[102] fbd[103] fbd[121] fbd[120] p fbd[80] fbd[71] fbd[78] fbd[79] vdd vdd fbd[100] fbd[101] fbd[123] fbd[122] r fbd[70] fbd[69] fbd[88] fbd[89] nic nic fbd[98] fbd[99] fbd[125] fbd[124] t fbd[68] fbd[67] fbd[90] vdd nic hostvdd hostvdd host- clamp hostvdd host- clamp hostvdd host- clamp vdd fbd[97] fbd[127] fbd[126] u fbd[66] fbd[65] fbd[92] fbd[91] host- clamp xtalout pcirst# agpst[1] pciad[30] pciad[26] pcicbe#[3] pciad[20] pciad[16] pcitrdy# pcipar hostvdd pcicbe#[0] fbd[96] vidvsync vidhsync v fbd[64] fbd[95] red dacvdd vref pciinta# pcig nt# agppipe# pciad[28] pciad[24] pciad[22] pciad[18] pciframe# pcistop# pciad[15] pciad[11] pciad[6] pciad[2] testmode romcs# w fbd[93] fbd[94] blue comp pllvdd pcireq# agpst[2] pciad[31] pciad[27] agpad- stb1 * pciad[21] pciad[17] pciirdy# pcicbe#[1] pciad[13] pciad[9] pciad[4] pciad[0] pciad[7] pciad[5] y green gnd rset xtalin pciclk agpst[0] pciidsel/ agprbf# pciad[29] pciad[25] pciad[23] pciad[19] pcicbe#[2] pci- devsel# pciad[14] pciad[12] pciad[10] pciad[8] agpad- stb0 * pciad[3] pciad[1]
128-bit 3d multimedia accelerator riva 128 6/77 2 pin descriptions 2.1 accelerated graphics port (agp) interface 2.2 pci 2.1 local bus interface signal i/o description agpst[2:0] i agp status bus providing information from the arbiter to the riva 128 on what it may do. agpst[2:0] only have meaning to the riva 128 when pcignt# is asserted. when pcignt# is de-asserted these signals have no meaning and must be ignored. 000 indicates that previously requested low priority read or flush data is being returned to the riva 128. 001 indicates that previously requested high priority read data is being returned to the riva 128. 010 indicates that the riva 128 is to provide low priority write data for a previous enqueued write command. 011 indicates that the riva 128 is to provide high priority write data for a previous enqueued write command. 100 reserved 101 reserved 110 reserved 111 indicates that the riva 128 has been given permission to start a bus transac- tion. the riva 128 may enqueue agp requests by asserting agppipe# or start a pci transaction by asserting pciframe# . agpst[2:0] are always an output from the core logic (agp chipset) and an input to the riva 128. agprbf# o read buffer full indicates when the riva 128 is ready to accept previously requested low priority read data or not. when agprbf# is asserted the arbiter is not allowed to return (low priority) read data to the riva 128. this signal should be pulled up via a 4.7k w resis- tor (although it is supposed to be pulled up by the motherboard chipset). agppipe# o pipelined read is asserted by riva 128 (when the current master) to indicate a full width read address is to be enqueued by the target. the riva 128 enqueues one request each rising clock edge while agppipe# is asserted. when agppipe# is de-asserted no new requests are enqueued across pciad[31:0] . agppipe# is a sustained tri-state signal from the riva 128 and is an input to the target (the core logic). agpadstb0 *, agpadstb1 * i/o these signals are currently a ano-connecto in this revision of the riva 128 but may be acti- vated to support agp double-edge clocking in future pin compatible devices. it is recom- mended that these pins are connected directly to the ad_stb0 and ad_stb1 pins defined in the agp specification. signal i/o description pciclk i pci clock. this signal provides timing for all transactions on the pci bus, except for pcirst# and pciinta# . all pci signals are sampled on the rising edge of pciclk and all timing parameters are defined with respect to this edge. pcirst# i pci reset. this signal is used to bring registers, sequencers and signals to a consistent state. when pcirst# is asserted all output signals are tristated. pciad[31:0] i/o 32-bit multiplexed address and data bus. a bus transaction consists of an address phase followed by one or more data phases.
128-bit 3d multimedia accelerator riva 128 7/77 pcicbe[3:0]# i/o multiplexed bus command and byte enable signals. during the address phase of a trans- action pcicbe[3:0]# define the bus command, during the data phase pcicbe[3:0]# are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes contain valid data. pcicbe[0]# applies to byte 0 (lsb) and pcicbe[3]# applies to byte 3 (msb). when connected to agp these signals carry different commands than pci when requests are being enqueued using agppipe# . valid byte information is provided during agp write transactions. pcicbe[3:0]# are not used during the return of agp read data. pcipar i/o parity. this signal is the even parity bit generated across pciad[31:0] and pcicbe[3:0]# . pcipar is stable and valid one clock after the address phase. for data phases pcipar is stable and valid one clock after either pciirdy# is asserted on a write transaction or pcitrdy# is asserted on a read transaction. once pcipar is valid, it remains valid until one clock after completion of the current data phase. the master drives pcipar for address and write data phases; the target drives pcipar for read data phases. pciframe# i/o cycle frame. this signal is driven by the current master to indicate the beginning of an access and its duration. pciframe# is asserted to indicate that a bus transaction is beginning. data transfers continue while pciframe# is asserted. when pciframe# is deasserted, the transaction is in the final data phase. pciirdy# i/o initiator ready. this signal indicates the initiator's (bus master's) ability to complete the cur- rent data phase of the transaction. see extended description for pcitrdy# . when connected to agp this signal indicates the initiator (agp compliant master) is ready to provide all write data for the current transaction. once pciirdy# is asserted for a write operation, the master is not allowed to insert wait states. the assertion of pciirdy# for reads, indicates that the master is ready to transfer a subsequent block of read data. the master is never allowed to insert a wait state during the initial block of a read transaction. however, it may insert wait states after each block transfers. pcitrdy# i/o target ready. this signal indicates the target's (selected device's) ability to complete the current data phase of the transaction. pcitrdy# is used in conjunction with pciirdy# . a data phase is completed on any clock when both pcitrdy# and pciirdy# are sampled as being asserted. during a read, pcitrdy# indicates that valid data is present on pciad[31:0] . during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both pciirdy# and pcitrdy# are asserted together. when connected to agp this signal indicates the agp compliant target is ready to provide read data for the entire transaction (when transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data, when the transfer requires more than four clocks to complete. the target is allowed to insert wait states after each block transfers on both read and write transactions. pcistop# i/o pcistop# indicates that the current target is requesting the master to terminate the cur- rent transaction. pciidsel i initializat ion device select. this signal is used as a chip select during configuration read and write transactions. for agp applications note that idsel is not a pin on the agp connector. the riva 128 performs the device select decode internally within its host interface. it is not required to connect the ad16 signal to the idsel pin as suggested in the agp specification. pcidevsel# i/o device select. when acting as an output pcidevsel# indicates that the riva 128 has decoded the pci address and is claiming the current access as the target. as an input pcidevsel# indicates whether any other device on the bus has been selected. pcireq# o request. this signal is asserted by the riva 128 to indicate to the arbiter that it desires to become master of the bus. signal i/o description
128-bit 3d multimedia accelerator riva 128 8/77 2.3 sgram framebuffer interface 2.4 video port pcignt# i grant. this signal indicates to the riva 128 that access to the bus has been granted and it can now become bus master. when connected to agp additional information is provided on agpst[2:0] indicating that the master is the recipient of previously requested read data (high or low priority), it is to provide write data (high or low priority), for a previously enqueued write command or has been given permission to start a bus transaction (agp or pci). pciinta# o interrupt request line. this open drain output is asserted and deasserted asynchronously to pciclk . signal i/o description fbd[127:0] i/o the 128-bit sgram memory data bus. fbd[31:0] are also used to access up to 64kbytes of 8-bit rom or flash rom, using fbd[15:0] as address roma[15:0], fbd[31:24] as romd[7:0], fbd[17] as romwe# and fbd[16] as romoe#. fba[10:0] o memory address bus. configuration strapping options are also decoded on these signals during pcirst# as described in section 10, page 49. [fba[10] is reserved for future expansion and should be pulled to gnd via a 4.7k w resistor. fbras# o memory row address strobe for all memory devices. fbcas# o memory column address strobe for all memory devices. fbcs[1:0]# o memory chip select strobes for each sgram bank. fbwe# o memory write enable strobe for all memory devices. fbdqm[15:0] o memory data/output enable strobes for each of the 16 bytes. fbclk0, fbclk1, fbclk2 o memory clock signals. separate clock signals fbclk0 and fbclk1 are provided for each bank of sgram for reduced clock skew and loading. fbclk2 is fed back to fbclkfb . details of recommended memory clock layout are given in section 6.3, page 31. fbclkfb i framebuffer clock feedback. fbclk2 is fed back to fbclkfb . fbcke * o this signal is currently a ano-connecto in this revision of the riva 128 but may be activated to support the framebuffer memory clock enable for power management in future pin com- patible devices. it is recommended that this pin is tied to vdd through a 4.7k w pull-up resistor. signal i/o description mp_ad[7:0] i/o media port 8-bit multiplexed address and data bus or itu-r-656 video data bus when in 656 mode. mpclk i 40mhz media port system clock or pixel clock when in 656 mode. mpdtack# i media port data transfer acknowledgment signal. mpframe# o initiates media port transfers when active, terminates transfers when inactive. mpstop# i media port control signal used by the slave to terminate transfers. signal i/o description
128-bit 3d multimedia accelerator riva 128 9/77 2.5 device enable signals 2.6 display interface 2.7 video dac and pll analog signals 2.8 power supply signal i/o description romcs# o enables reads from an external 64kx 8 or 32kx8 rom or flash rom. this signal is used in conjunction with framebuffer data lines as described above in section 2.3. signal i/o description sda i/o used for ddc2b+ monitor communication and interface to video decoder devices. scl i/o used for ddc2b+ monitor communication and interface to video decoder devices. vidvsync o vertical sync supplied to the display monitor. no buffering is required. in tv mode this sig- nal supplies composite sync to an external pal/ntsc encoder. vidhsync o horizontal sync supplied to the display monitor. no buffering is required. signal i/o description red, green, blue o rgb display monitor outputs. these are software configurable to drive either a doubly ter- minated or singly terminated 75 w load. comp - external compensation capacitor for the video dacs. this pin should be connected to dacvdd via the compensation capacitor, see figure 58, page 54. rset - a precision resistor placed between this pin and gnd sets the full-scale video dac cur- rent, see figure 58, page 54. vref - a capacitor should be placed between this pin and gnd as shown in figure 58, page 54. xtalin i a series resonant crystal is connected between these two points to provide the reference clock for the internal mclk and vclk clock synthesizers, see figure 58 and table 16, page 54. alternately, an external lvttl clock oscillator output may be driven into xta- lout , connecting xtalin to gnd. for designs supporting tv-out, xtalout should be driven by a reference clock as described in section 11.6, page 55. xtalout o signal i/o description dacvdd p analog power supply for the video dacs. pllvdd p analog power supply for all clock synthesizers. vdd p digital power supply. gnd p ground. mpclamp p mpclamp is connected to +5v to protect the 3.3v riva 128 from external devices which will potentially drive 5v signal levels onto the video port input pins. hostvdd p hostvdd is connected to the vddq 3.3 pins on the agp connector. this is the supply voltage for the i/o buffers and is isolated from the core vdd. on agp designs these pins are also connected to the hostclamp pins. on pci designs they are connected to the 3.3v supply. hostclamp p hostclamp is the supply signalling rail protection for the host interface. in agp designs these signals are connected to vddq 3.3. for pci designs they are connected to the i/o power pins (v (i/o) ).
128-bit 3d multimedia accelerator riva 128 10/77 2.9 test signal i/o description testmode i for designs which will be tested in-circuit, this pin should be connected to gnd through a 10k w pull-down resistor, otherwise this pin should be connected directly to gnd. when testmode is asserted, mp_ad[3:0] are reassigned as testctl[3:0] respectively. information on in-circuit test is given in section 12, page 57.
128-bit 3d multimedia accelerator riva 128 11/77 3 overview of the riva 128 the riva 128 is the first 128-bit 3d multimedia accelerator to offer unparalleled 2d and 3d perfor- mance, meeting all the requirements of the main- stream pc graphics market and microsoft's pc'97. the riva 128 introduces the most ad- vanced direct3d ? acceleration solution and also delivers leadership vga, 2d and video perfor- mance, enabling a range of applications from 3d games through to dvd, intercast ? and video con- ferencing. 3.1 balanced pc system the riva 128 is designed to leverage existing pc system resources such as system memory, high bandwidth internal buses and bus master capabil- ities. the synergy between the riva 128 graphics pipeline architecture and that of the current gener- ation pci and next generation agp platforms, de- fines ground breaking performance levels at the cost point currently required for mainstream pc graphics solutions. execute versus dma models the riva 128 is architected to optimize pc sys- tem resources in a manner consistent with the agp aexecuteo model . in this model texture map data for 3d applications is stored in system mem- ory and individual texels are accessed as needed by the graphics pipeline. this is a significant en- hancement over the dma model where entire tex- ture maps are transferred into off-screen frame- buffer memory. the advantages of the execute versus the dma model are: ? improved system performance since only the required texels and not the entire texture map, cross the bus. ? substantial cost savings since all the framebuff- er is usable for the displayed screen and z buff- er and no part of it is required to be dedicated to texture storage or texture caching. ? there is no software overhead in the direct3d driver to manage texture caching between ap- plication memory and the framebuffer. to extend the advantages of the execute model, the riva 128's proprietary texture cache and vir- tual dma bus master design overcomes the band- width limitation of pci, by sustaining a high texel throughput with minimum bus utilization. the host interface supports burst transactions up to 66mhz and provides over 200mbytes/s on agp. agp ac- cesses offer other performance enhancements since they are from non-cacheable memory (no snoop) and can be low priority to prevent proces- sor stalls, or high priority to prevent graphics en- gine stalls. building a balanced system riva 128 is architected to provide the level of 3d graphics performance and quality available in top arcade platforms. to provide comparable scene complexity in the 1997 time-frame, processors will have to achieve new levels of floating point perfor- mance. profiles have shown that 1997 main- stream cpus will be able to transform over 1 mil- lion lit, meshed triangles/s at 50% utilization using direct3d. this represents an order of magnitude performance increase over anything attainable in 1996 pc games. to build a balanced system the graphics pipeline must match the cpu's performance. it must be ca- pable of rendering at least 1 million polygons/s in order to avoid cpu stalls. factors affecting this system balance include: ? direct3d compatibility. minimizing the differ- ences between the hardware interface and the direct3d data structures. ? triangle setup. minimizing the number of for- mat conversions and delta calculations done by the cpu. ? display-list processing. avoiding cpu stalls by allowing the graphics pipeline to execute inde- pendently of the cpu. ? vertex caching. avoids saturating the host in- terface with repeated vertices, lowering the traf- fic on the bus and reducing system memory col- lisions. ? host interface performance. 3.2 host interface the host interface boosts communication between the host cpu and the riva 128. the optimized in- terface performs burst dma bus mastering for ef- ficient and fast data transfer. ? 32-bit pci version 2.1 or agp version 1.0 ? burst dma master and target ? 33mhz pci clock rate or 66mhz agp clock rate ? supports over 100mbytes/s with 33mhz pci and over 200mbytes/s on 66mhz agp ? implements read buffer posting on agp ? fully supports the aexecuteo model on both pci and agp
128-bit 3d multimedia accelerator riva 128 12/77 3.3 2d acceleration the riva 128's 2d rendering engine delivers in- dustry-leading windows acceleration perfor- mance: ? 100mhz 128-bit graphics engine optimized for single cycle operation into the 128-bit sgram interface supporting up to 1.6gbytes/s ? acceleration functions optimized for minimal software overhead on key gdi calls ? extensive support for directdraw in windows95 including optimized direct frame- buffer (dfb) access with write-combining ? accelerated primitives including blt, transpar- ent blt, stretchblt, points, lins, lines, polylines, polygons, fills, patterns, arbitrary rectangular clipping and improved text render- ing ? pipeline optimized for multiple color depths in- cluding 8, 15, 24, and 30 bits per pixel ? dma pusher allows the 2d graphics pipeline to load rendering methods optimizing riva 128/ host multi-tasking ? execution of all 256 raster operations (as de- fined by microsoft windows) at 8, 15, 24 and 30-bit color depths ? 15-bit hardware color cursor ? hardware color dithering ? multi buffering (double, triple, quad buffering) for smooth animation 3.4 3d engine triangle setup engine ? setup hardware optimized for microsoft's direct3d api ? 5gflop floating point geometry processor ? slope and setup calculations ? accepts ieee single precision format used in direct3d ? efficient vertex caching rendering engine the riva 128 multimedia accelerator integrates an orthodox 3d rendering pipeline and triangle setup function which not only fully utilizes the ca- pabilities of the accelerated graphics port, but also supports advanced texture mapped 3d over the pci bus. the riva 128 3d pipeline offers to direct3d or similar apis advanced triangle render- ing capabilities: ? rendering pipeline optimized for microsoft's direct3d api ? perspective correct true-color gouraud lighting and texture mapping ? full 32-bit rgba texture filter and gouraud lighting pixel data path ? alpha blending for translucency and transpar- ency ? sub-pixel accurate texture mapping ? internal pixel path: up to 24bits, alpha: up to 8 bits ? texture magnification filtering with high quality bilinear filtering without performance degrada- tion ? texture minification filtering with mip mapping without performance degradation ? lod mip-mapping: filter shape is dynamically adjusted based on surface orientation ? texture sizes from 4 to 2048 texels in either u or v ? textures can be looped and paged in real time for texture animation ? perspective correct per-pixel fog for atmo- spheric effects ? perspective correct specular highlights ? multi buffering (double, triple, quad buffering) for smooth 3d animation ? multipass rendering for environmental mapping and advanced texturing 3.5 video processor the riva 128 palette-dac pipeline accelerates full-motion video playback, sustaining 30 frames per second while retaining the highest quality color resolution, implementing true bilinear filtering for scaled video, and compensating for filtering losses using edge enhancement algorithms. ? advanced support for directdraw (directvideo) in windows 95 ? back-end hardware video scaling for video con- ferencing and playback ? hardware color space conversion (yuv 4:2:2 and 4:2:0) ? multi-tap x and y filtering for superior image quality ? optional edge enhancement to retain video sharpness ? support for scaled field interframing for reduced motion artifacts and reduced storage
128-bit 3d multimedia accelerator riva 128 13/77 ? per-pixel color keying ? multiple video windows with hardware color space conversion and filtering ? planar yuv12 (4:2:0) to/from packed (4:2:2) conversion for software mpeg acceleration and h.261 video conferencing applications ? accelerated playback of industry standard co- decs including mpeg-1/2, indeo, cinepak 3.6 video port the riva 128 multimedia accelerator provides connectivity for video input devices such as philips saa7111a, itt 3225 and samsung ks0127 through an itu-r-656 video input bus to dvd and mpeg2 decoders through bidirectional media port functionality. ? supported through vpe extensions to directdraw ? supports filtered down-scaling and decimation ? supports real time video capture via bus mas- tering dma ? serial interface for decoder control 3.7 direct rgb output to low cost pal/ntsc encoder the riva 128 has also been designed to interface to a standard pal or ntsc television via a low cost tv encoder chip. in pal or ntsc display modes the interlaced output is internally flicker-fil- tered and ccir/eia compliant timing reference signals are generated. 3.8 support for standards ? multimedia support for ms-dos, windows 3.11, windows 95, and windows nt ? acceleration for windows 95 direct apis in- cluding direct3d, directdraw and directvideo ? vga and svga: the riva 128 has an industry standard 32-bit vga core and bios support. in pci configuration space the vga can be en- abled and disabled independently of the gui. ? glue-less accelerated graphics port (agp 1.0) or pci 2.1 bus interface ? itu/ccir-656 compatible video port ? vesa ddc2b+, dpms, vbe 2.0 supported 3.9 resolutions supported resolution bpp 2mbyte 4mbyte (128-bit) 640x480 4 120hz 120hz 8 120hz 120hz 16 120hz 120hz 32 120hz 120hz 800x600 4 120hz 120hz 8 120hz 120hz 16 120hz 120hz 32 120hz 120hz 1024x76 8 4 120hz 120hz 8 120hz 120hz 16 120hz 120hz 32 - 120hz 1152x86 4 4 120hz 120hz 8 120hz 120hz 16 120hz 120hz 32 - 100hz 1280x10 24 4 100hz 100hz 8 100hz 100hz 16 - 100hz 32 - - 1600x12 00 4 75hz 75hz 8 75hz 75hz 16 - 75hz 32 - -
128-bit 3d multimedia accelerator riva 128 14/77 3.10 customer evaluation kit a customer evaluation kit (cek) is available for evaluating the riva 128. the cek includes a pci or agp adapter card designed to support the riva 128 feature set, an evaluation cd-rom contain- ing a fast-installation application, extensive device drivers and programs demonstrating the riva 128 features and performance. this cek includes: ? riva 128 evaluation board and cd-rom ? quickstart install/user guide ? os drivers and files - windows 3.11 - windows 95 direct x/3d - windows nt 3.5 - windows nt 4.0 ? demonstration files and game demos ? benchmark programs and files 3.11 turnkey manufacturing package a turnkey manufacturing package (tmp) is avail- able to support oem designs and development through to production. it delivers a complete man- ufacturable hardware and software solution that allows an oem to rapidly design and bring to vol- ume an riva 128-based product. this tmp includes: ? cd-rom - riva 128 datasheet and application notes - orcad ? schematic capture and pads ? layout design information - quick start install/user guide/release notes - bios modification program, bios binaries and utilities - bring-up and oem production diagnostics - software and utilities ? os drivers and files - windows 3.11 - windows 95 direct x/3d - windows nt 3.5 - windows nt 4.0 ? fcc/ce certification package ? content developer and www information ? partner solutions ? access to our password-protected web site for upgrade files and release notes.
128-bit 3d multimedia accelerator riva 128 15/77 4 accelerated graphics port (agp) interface the accelerated graphics port (agp) is a high performance, component level interconnect targeted at 3d graphical display applications and based on performance enhancements to the pci local bus. figure 1. system block diagram showing relationship between agp and pci buses background to agp although 3d graphics acceleration is becoming a standard feature of multimedia pc platforms, 3d rendering generally has a voracious appetite for memory bandwidth. consequently there is upward pressure on the pc's memory requirement leading to higher bill of material costs. these trends will in- crease, requiring high speed access to larger amounts of memory. the primary motivation for agp therefore was to contain these costs whilst enabling performance improvements. by providing significant bandwidth improvement between the graphics accelerator and system memory, some of the 3d rendering data structures can be shifted into main memory, thus relieving the pressure to increase the cost of the local graphics memory. texture data are the first structures targeted for shifting to system memory for four reasons: 1 textures are generally read only, and therefore do not have special access ordering or coher- ency problems. 2 shifting textures balances the bandwidth load between system memory and local graphics memory, since a well cached host processor has much lower memory bandwidth require- ments than a 3d rendering engine. texture ac- cess comprises perhaps the largest single com- ponent of rendering memory bandwidth (com- pared with rendering, display and z buffers), so avoiding loading or caching textures in graphics local memory saves not only this component of local memory bandwidth, but also the band- width necessary to load the texture store in the first place. furthermore, this data must pass through main memory anyway as it is loaded from a mass store device. 3 texture size is dependent upon application quality rather than on display resolution, and therefore subject to the greatest pressure for growth. 4 texture data is not persistent; it resides in memory only for the duration of the application, so any system memory spent on texture stor- age can be returned to the free memory heap when the application finishes (unlike display buffers which remain in use). other data structures can be moved to main mem- ory but the biggest gain results from moving tex- ture data. relationship of agp to pci agp is a superset of the 66mhz pci specification (revision 2.1) with performance enhancements optimized for high performance 3d graphics appli- cations. the pci specification is unmodified by agp and `reserved' pci fields, encodings and pins, etc. are not used. agp does not replace the need for the pci bus in the system and the two are physically, logically, and electrically independent. as shown in figure 1 agp chipset riva 128 system memory cpu i/o i/o i/o pci agp
128-bit 3d multimedia accelerator riva 128 16/77 the agp bridge chip and riva 128 are the only devices on the agp bus - all other i/o devices re- main on the pci bus. the add-in slot defined for agp uses a new con- nector body (for electrical signaling reasons) which is not compatible with the pci connector; pci and agp boards are not mechanically inter- changeable. agp accesses differ from pci in that they are pipelined. this compares with serialized pci transactions, where the address, wait and data phases need to complete before the next transac- tion starts. agp transactions can only access sys- tem memory - not other pci devices or cpu. bus mastering accesses can be either pci or agp- style. full details of agp are given in the accelerated graphics port interface specification [3] published by intel corporation. 4.1 riva 128 agp interface the riva 128 glueless interface to agp 1.0 is shown in figure 2. figure 2. agp interface pin connections 4.2 agp bus transactions agp bus commands supported the following agp bus commands are supported by the riva 128: - read - read (hi-priority) pci transactions on the agp bus pci transactions can be interleaved with agp transactions including between pipelined agp data transfers. a basic pci transaction on the agp interface is shown in figure 3. if the pci target is a non agp compliant master, it will not see agpst[2:0] and the transaction appears to be on a pci bus. for agp aware bus masters, agpst[2:0] indicate that permission to use the in- terface has been granted to initiate a request and not to move agp data. agp bus pcicbe[3:0]# pciad[31:0] agppipe# 32 4 pcidevsel# pciirdy# pcitrdy# pcistop# pciidsel pcireq# pcignt# pciclk pcirst# pcipar pciinta# riva 128 agpst[2:0]# 3 agprbf#
128-bit 3d multimedia accelerator riva 128 17/77 figure 3. basic pci transaction on agp an example of a pci transaction occurring between an agp command cycle and return of data is shown in figure 4. this shows the smallest number of cycles during which an agp request can be enqueued, a pci transaction performed and agp read data returned. figure 4. pci transaction occurring between agp request and data bus cmd data_pci address be[3:0]# 111 111 xxx xxx xxx xxx pciclk pciframe# pciad[31:0] pcicbe[3:0]# pciirdy# pcitrdy# pcidevsel# pcireq# pcignt# agpst[2:0] 13456 2 a9 111 xxx 111 111 xxx 111 address data d7 +1 c9 pci_cmd be 0000 000 xxx 00x xxx xxx pciclk agppipe# pciframe# pciad[31:0] pcicbe# pciirdy# pcitrdy# pcidevsel# pciagprbf# pcireq# pcignt# agpst[2:0] 12345678910
128-bit 3d multimedia accelerator riva 128 18/77 figure 5. basic agp pipeline concept pipeline operation memory access pipelining provides the main per- formance enhancement of agp over pci. agp pipelined bus transactions share most of the pci signal set, and are interleaved with pci transac- tions on the bus. the riva 128 supports agp pipelined reads with a 4-deep queue of outstanding read requests. pipelined reads are primarily used by the riva 128 for cache filling, the cache size being opti- mized for agp bursts. depending on the agp bridge, a bandwidth of up to 248mbyte/s is achiev- able for 128-byte pipelined reads. this compares with around 100mbyte/s for 128-byte 33mhz pci reads. another feature of agp is that for smaller sized reads the bandwidth is not significantly re- duced. whereas 16-byte reads on pci transfer at around 33mbyte/s, on agp around 175mbyte/s is achievable. the riva 128 actually requests reads greater than 64 bytes in multiples of 32-byte trans- actions. the pipe depth can be maintained by the agp bus master (riva 128) intervening in a pipelined trans- fer to insert new requests between data replies. this bus sequencing is illustrated in figure 5. when the bus is in an idle condition, the pipe can be started by inserting one or more agp access requests consecutively. once the data reply to those accesses starts, that stream can be broken (or intervened) by the bus master (riva 128) in- serting one or more additional agp access re- quests or inserting a pci transaction. this inter- vention is accomplished with the bus ownership signals, pcireq# and pcignt# . the riva 128 implements both high and low prior- ity reads depending of the status of the rendering engine. if the pipeline is likely to stall due to sys- tem memory read latency, a high priority read re- quest is posted. address transactions the riva 128 requests permission from the bridge to use pciad[31:0] to initiate either an agp request or a pci transaction by asserting pcireq# . the arbiter grants permission by as- serting pcignt# with agpst[2:0] equal to `111' (referred to as start). when the riva 128 re- ceives start it must start the bus operation with- in two clocks of the bus becoming available. for example, when the bus is in an idle condition when start is received, the riva 128 must initiate the bus transaction on the next clock and the one fol- lowing. figure 6 shows a single address being enqueued by the riva 128. sometime before clock 1, the riva 128 asserts pcireq# to gain permission to use pciad[31:0] . the arbiter grants permission by indicating start on clock 2. a new request (address, command and length) are enqueued on each clock in which agppipe# is asserted. the address of the request to be enqueued is present- ed on pciad[31:3] , the length on pciad[2:0] and the command on pcicbe[3:0]# . in figure 6 only a single address is enqueued since agppipe# is just asserted for a single clock. the riva 128 in- dicates that the current address is the last it in- tends to enqueue when agppipe# is asserted and pcireq# is deasserted (occurring on clock 3). once the arbiter detects the assertion of agp- pipe# or pciframe# it deasserts pcignt# on clock 4. bus idle pipelined data transfer intervene cycles pipelined agp requests a1 a2 data-1 data-2 a3 pci transaction a data data-3
128-bit 3d multimedia accelerator riva 128 19/77 figure 6. single address - no delay by master figure 7 shows the riva 128 enqueuing 4 requests, where the first request is delayed by the maximum 2 cycles allowed. start is indicated on clock 2, but the riva 128 does not assert agppipe# until clock 4. note that pcireq# remains asserted on clock 6 to indicate that the current request is not the last one. when pcireq# is deasserted on clock 7 with agppipe# still asserted this indicates that the current ad- dress is the last one to be enqueued during this transaction. agppipe# must be deasserted on the next clock when pcireq# is sampled as deasserted. if the riva 128 wants to enqueue more requests during this bus operation, it continues asserting agppipe# until all of its requests are enqueued or until it has filled all the available request slots provided by the target. figure 7. multiple addresses enqueued, maximum delay by riva 128 c1 a1 111 111 xxx xxx xxx xxx xxx xxx pciclk agppipe# pciad[31:0] pcicbe[3:0]# pcireq# pcignt# agpst[2:0] 12345678 a1 111 111 111 xxx xxx xxx xxx xxx a2 a3 a4 c1 c2 c3 c4 pciclk agppipe# pciad[31:0] pcicbe# pcireq# pcignt# agpst[2:0] 1234567
128-bit 3d multimedia accelerator riva 128 20/77 agp timing specification figure 8. agp clock specification table 1. agp clock timing parameters notes 1 this rise and fall time is measured across the minimum peak-to-peak range as shown in figure 8. figure 9. agp timing diagram table 2. agp timing parameters symbol parameter min. max. unit notes t cyc pciclk period 15 30 ns t high pciclk high time 6 ns t low pciclk low time 6 ns pciclk slew rate 1.5 4 v/ns 1 symbol parameter min. max. unit notes t val agpclk to signal valid delay (data and control signals) 211ns t on float to active delay 2 ns t off active to float delay 28 ns t su input set up time to agpclk (data and control signals) 7ns t h input hold time from agpclk 0ns t cyc t high t low pciclk 0.3vdd 0.4vdd 0.5vdd 0.2vdd 0.6vdd 2v p-to-p (minimum) t val t val t on t off t su t h data1 data2 data1 data2 agpclk output delay tri-state output input
128-bit 3d multimedia accelerator riva 128 21/77 5 pci 2.1 local bus interface 5.1 riva 128 pci interface the riva 128 supports a glueless interface to pci 2.1 with both master and slave capabilities. the host interface is fully compliant with the 32-bit pci 2.1 specification. the multimedia accelerator supports pci bus operation up to 33mhz with zero-wait state capability and full bus mastering capability handling burst reads and burst writes. figure 10. pci interface pin connections table 3. pci bus commands supported by the riva 128 bus master bus slave memory read and write memory read and write memory read line i/o read and write memory read multiple configuration read and write memory read line memory read multiple memory write invalidate pci bus pcicbe[3:0]# pciad[31:0] pciframe# 32 4 pcidevsel# pciirdy# pcitrdy# pcistop# pciidsel pcireq# pcignt# pciclk pcirst# pcipar pciinta# riva 128
128-bit 3d multimedia accelerator riva 128 22/77 5.2 pci timing specification the timing specification of the pci interface takes the form of generic setup, hold and delay times of tran- sitions to and from the rising edge of pciclk as shown in figure 11. figure 11. pci timing parameters table 4. pci timing parameters note 1 pcireq# and pcignt# are point to point signals and have different valid delay and input setup times than bussed sig- nals. all other signals are bussed. symbol parameter min. max. unit notes t val pciclk to signal valid delay (bussed signals) 2 11 ns 1 t val (ptp) pciclk to signal valid delay (point to point) 2 12 ns 1 t on float to active delay 2 ns t off active to float delay 28 ns t su input set up time to pciclk (bussed signals) 7 ns 1 t su (ptp) input set up time to pciclk ( pcignt# )10 ns1 t su (ptp) input set up time to pciclk ( pcireq# )12 ns t h input hold time from pciclk 0ns t val t on t off t su t h pciclk output delay tri-state output input pciclk output timing parameters input timing parameters
128-bit 3d multimedia accelerator riva 128 23/77 figure 12. pci target write - slave writ e (single 32-bit with 1-cycle devsel# response) figure 13. pci target write - slave write (multiple 32-bit with zero wait state devsel# response) address data bus cmd be[3:0]# (med) pciclk pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel# address data0 bus cmd be[3:0]# data1 data2 be[3:0]# be[3:0]# pciclk pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel#
128-bit 3d multimedia accelerator riva 128 24/77 figure 14. pci target read - slave read (1-cycle single word read) figure 15. pci target read - slave read (slow single word read) address bus cmd be[3:0]# data0 pciclk pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel# address bus cmd be[3:0]# data0 pciclk pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel#
128-bit 3d multimedia accelerator riva 128 25/77 figure 16. pci master write - multiple word figure 17. pci master read - multiple word note: the riva 128 does not gene rate fast back to back cycles as a bus master bus cmd data0 data1 address data2 data3 be[3:0]# be[3:0]# be[3:0]# be[3:0]# pciclk pcireq# pcignt# pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel# bus cmd data0 address data1 be[3:0]# be[3:0]# pciclk pcireq# pcignt# pciad[31:0] pcicbe[3:0]# pciframe# pciirdy# pcitrdy# pcidevsel#
128-bit 3d multimedia accelerator riva 128 26/77 figure 18. pci target configuration cycle - slave configuration write figure 19. pci target configuration cycle - slave configuration read bus cmd be[3:0]# data0 address (med) pciclk ad[31:0] pcicbe[3:0]# pciframe# pciidsel pciirdy# pcitrdy# pcidevsel# bus cmd be[3:0]# config_data address pciad[31:0] pcicbe[3:0]# pciframe# pciidsel pciirdy# pcitrdy# pcidevsel# (med) pciclk
128-bit 3d multimedia accelerator riva 128 27/77 figure 20. pci basic arbitration cycle figure 21. target initiated termination address data address data access a access b pciclk pcireq#_a pcireq#_b pcignt#_a pcignt#_b pciframe# pciad[31:0] 123 4 1234 123 4 12345 disconnect - a disconnect - b disconnect - c / retry target - abort pciclk pciframe# pciirdy# pcitrdy# pcistop# pcidevsel# pciclk pciframe# pciirdy# pcitrdy# pcipcistop# pcidevsel#
128-bit 3d multimedia accelerator riva 128 28/77 6 sgram framebuffer interface the riva 128 sgram interface can be configured with a 2mbyte 64-bit or 4mbyte 128-bit data bus. with a 128-bit bus, 4mbytes of sgram is supported as shown in figure 22. all of the sgram signalling envi- ronment is 3.3v. figure 22. 64-bit 2mbyte and 128-bit 4mbyte sgram configurations read and write accesses to sgram are burst oriented. sgram commands supported by the riva 128 are shown in table 5. initialization of the memory devices is performed in the standard sgram manner as described in section 6.1. access sequences begin with an active command followed by a read or write command. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the riva 128 always uses a burst length of one and can launch a new read or write on every cycle. sgram has a fully synchronous interface with all signals registered on the positive edge of fbclkx. mul- tiple clock outputs allow reductions in signal loading and more accuracy in data sampling at high frequen- cy. the clock signals can be interspersed as shown in figure 23, page 29 for optimal loading with either 2 or 4mbytes. the i/o timings relative to fbclkx are shown in figure 25, page 31. riva 128 256k x32 256k x32 fbd[31:0] fbd[63:32] 256k x32 fbd[95:64] 256k x32 fbd[127:96] expansion to 4mbytes
128-bit 3d multimedia accelerator riva 128 29/77 figure 23. 2 and 4mbyte sgram configurations note 1 riva 128 has a pin reserved for an eleventh addre ss signal, fba[10] , which may be used in the future with pin compatible 16mbit 256k x 2 x 32 sdrams. this signal is a ano-connecto in the initial riva 128 but may be activated in a future pin- compatible upgrade .if there is sufficient routing space it may be pruden t to route this signal to pin 30 of the 100 pin pqfp sgram. [fba10] should be pulled to gnd with a 47k w resistor. fbd[127:0] fbdqm[0]# fbdqm[1]# 256k 32 sgram fbd[31:0] fbd[63:32] fbdqm[2]# fbdqm[3]# fbdqm[4]# fbdqm[5]# 256k 32 sgram fbdqm[6]# fbdqm[7]# fbdqm[8]# fbdqm[9]# fbdqm[10]# fbdqm[11]# fbdqm[12]# fbdqm[13]# fbdqm[14]# fbdqm[15]# fbd[95:64] fbd[127:96] 256k 32 sgram fbcs[0]# fbclk1 fbcs[0]# fbclk0 fbcs[1]# fbclk1 fbcs[1]# fbclk0 256k 32 sgram fbcke# fbcas# fbwe# fbras# fba[9:0] fba[10] 1 fbcke# fbcas# fbwe# fbras# fba[9:0] fba[10] 1 expansion to 4mbytes
128-bit 3d multimedia accelerator riva 128 30/77 table 5. truth table of supported sgram commands notes 1 fbck e is high and dsf is low for all supported commands. 2 activates or deactivates fbd[12 7:0] during writes (zero clock delay) and read s (two-clock delay). 6.1 sgram initialization sgrams must be powered-up and initialized in a predefined manner. the first sgram command is reg- istered on the first clock edge following pcirst# inactive. all internal sgram banks are precharged to bring the device(s) into the aall bank idleo state. the sgram mode registers are then programmed and loaded to bring them into a defined state before performing any operational command. 6.2 sgram mode register the mode register defines the mode of operation of the sgram. this includes burst length, burst type, read latency and sgram operating mode. the mode register is programmed via the load mode register and retains its state until reprogrammed or power-down. mode register bits m[2:0] specify the burst length; for the riva 128 sgram interface these bits are set to zero, selecting a burst length of one. in this case fba[7:0] select the unique column to be accessed and mode register bit m[3] is ignored. mode register bits m[6:4] specify the read latency; for the riva 128 sgram interface these bits are set to either 2 or 3, selecting a burst length of 2 or 3 respectively. command 1 fbcsx fbras# fbcas# fbwe# fbdqm fba[9:0] fbd[63:0] notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) llhhx fba[9] =bank fba[8:0] =row x read (select bank and column and start read burst) lhlhx fba[9] =bank fba[8] =0 fba[7:0] =row x write (select bank and column and start write burst) lhll x fba[9] =bank fba[8] =0 fba[7:0] =row valid data precharge (deactivate row in both banks) llhlx fba[8] =1 x load mode register llllx fba[8:0] = opcode write enable/output enable - - - - l - active 2 write inhibit/output high-z - - - - h - high-z 2
128-bit 3d multimedia accelerator riva 128 31/77 6.3 layout of framebuffer clock signals separate clock signals fbclk0 and fbclk1 are provided for each bank of sgram to give reduced clock skew and loading. additionally there is a clock feedback loop between fbclk2 and fbclkfb . it is recommended that long traces are used without tunable components. if the layout includes provision for expansion to 4mbytes, the clock path to the 2mbyte parts should be at the end of the trace, and the clock path to the 4mbyte expansion located between the riva 128 and the 2mbyte parts as shown in fig- ure 24. fbclk2 and fbclkfb should be shorted together as close to the package as possible and con- nected via a 150 w resistor to vcc (3.3v), again as close to the package as possible. figure 24. recommended memory clock layout 6.4 sgram interface timing specification figure 25. sgram i/o timing diagram table 6. sgram i/o timing parameters symbol parameter min. max. unit notes -10 -12 -10 -12 t ck clk period 10 12 - - ns t ch clk high time 3.5 4.5 - - ns riva 128 256k x32 256k x32 256k x32 256k x32 bank 1 bank 0 expansion to 4mbytes fbclk0 fbclk1 t t fbclk2 fbclkfb vdd (3.3v) 150 w t ch t ck t cl t as ,t ds t ah ,t dh t lz t ac t oh fbclkx fba[9:0], fbd[63:0] fbd[63:0]
128-bit 3d multimedia accelerator riva 128 32/77 figure 26. sgram random read accesses within a page, read latency of two 1 note 1 covers either successive reads to the active row in a given bank, or to the active rows in different banks. dqms are all active (low). figure 27. sgram random read accesses within a page, read latency of three 1 note 1 covers either successive reads to the active row in a given bank, or to the active row s in different banks. fbdq m is all active (low). t cl clk low time 3.5 4.5 - - ns t as address setup time 3 4 - ns t ah address hold time 1 1 - ns t ds write data setup time 3 4 - ns t dh write data hold time 1 1 - ns t oh read data hold time 3 3 - ns t ac read data access time 9 9 - ns t lz data out low impedance time 0 0 - ns symbol parameter min. max. unit notes -10 -12 -10 -12 read read read data n data a read nop nop bank, col n bank, col a bank, col x bank, col m data x data m fbclkx command fba[9:0] fbd[63:0] read read read data n read nop nop bank, col n bank, col a bank, col x bank, col m data a data x data m nop fbclkx command fba[9:0] fbd[63:0]
128-bit 3d multimedia accelerator riva 128 33/77 figure 28. sgram read to write, read latency of three table 7. sgram i/o timing parameters figure 29. sgram random write cycles within a page note 1 covers either successive writes to the active row in a given bank or to the active row s in different banks. fbdq m is active (low). figure 30. sgram write to read cycle note 1 a read latency of 2 is shown for illustration symbol parameter min. max. unit notes t hz data out high impedance time 4 10 ns t ds write data setup time 4 ns t hz t ds read nop nop read data n nop write bank, col n write data b bank, col b fbclkx tddqm command fba[9:0] fbd[63:0] write write write write data n data a data x data m bank, col n bank, col a bank, col x bank, col m fbclkx command fba[9:0] fbd[63:0] write nop read nop nop nop bank, col n bank, col b write data n write data n read data b fbclkx command fba[9:0] fbd[63:0]
128-bit 3d multimedia accelerator riva 128 34/77 figure 31. sgram read to precharge, read latency of two note 1 fbdq m is active (low) figure 32. sgram read to precharge, read latency of three note 1 fbdq m is active (low) figure 33. sgram write to precharge nop active bank(s) bank,row data n t rp read prechar ge nop bank, col n fbclkx command fba[9:0] fbd[63:0] precharge nop nop active bank(s) bank, data n t rp read bank, fbclkx command fba[9:0] fbd[63:0] col n row write nop nop precharge nop nop active bank(s) row t rp t wr bank, col n write data n write data n+1 fbclkx fbdqm# command fba[9:0 ] fbd[63:0]
128-bit 3d multimedia accelerator riva 128 35/77 figure 34. sgram active to read or write table 8. sgram timing parameters symbol parameter min. max. unit notes t cs fbcsx , fbras# , fbcas# , fbwe# , fbdqm setup time 3ns t ch fbcsx , fbras# , fbcas# , fbwe# , fbdqm hold time 1ns t mtc load mode register command to command 2 t ck t ras active to precharge command period 7 t ck t rc active to active command period 10 t ck t rcd active to read or write delay 3 t ck t ref refresh period (1024 cycles) 16 ms t rp precharge command period 4 t ck t rrd active bank a to active bank b command period 3t ck t t transition time 1 ns t wr write recovery time 2 t ck active nop nop t rcd read or write fbclkx command
128-bit 3d multimedia accelerator riva 128 36/77 7 video playback architecture the riva 128 video playback architecture is de- signed to allow playback of ccir pal or ntsc video formats with the highest quality while requir- ing the smallest video surface. the implementa- tion is optimized around the windows 95 direct video and activex apis, and supports the follow- ing features: ? accepts interlaced video fields: - this allows the off-screen video surface to consume less memory since only one field (half of each frame) is stored. double buffer- ing between fields is done in hardware with `temporal averaging' being applied based on intraframing. ? linestore: - to support high quality video playback the riva 128 memory controller and video over- lay engine supports horizontal and vertical interpolation using a 3x2 multitap interpolat- ing filter with image sharpening. ? yuv to rgb conversion: - yuv 4:2:2 format to 24-bit rgb true-color - chrominance optimization/user control ? color key video composition figure 35. video scaler pipeline yuv vertical interpolation filter (smooth/sharpen) color space conversion to 24-bit rgb horizontal interpolation 24-bit rgb video output video windowing, merge with graphics pixel pipeline linestore
128-bit 3d multimedia accelerator riva 128 37/77 7.1 video scaler pipeline the riva 128 video scaler pipeline performs stretching of video images in any arbitrary factor in both horizontal and vertical directions. the video scaler pipeline consists of the following stages: 1 vertical stretching 2 filtering 3 color space conversion 4 horizontal stretching vertical stretching vertical stretching is performed on pixels prior to color conversion. the video scaler linearly interpo- lates the pixels in the vertical direction using an in- ternal buffer which stores the previous line of pixel information. filtering after vertical interpolation, the pixels are horizon- tally filtered using an edge-enhancement or a smoothing filter. the edge-enhancement filter en- hances picture transition information to prevent loss of image clarity following the smoothing filter- ing stage. the smoothing filter is a low-pass filter that reduces the noise in the source image. color space conversion the video overlay pipeline logic converts images from yuv 4:2:2 format to 24-bit rgb true-color. the default color conversion coefficients convert from ycrcb to gamma corrected rgb. saturation controls make sure that the conversion does not exceed the output range. four control flags in the color converter provides 16 sets of col- or conversion coefficients to allow adjustment of the hue and saturation. the brightness of each r g b component can also be individually adjust- ed, similar to the brightness controls of the moni- tor. horizontal stretching horizontal stretching is done in 24-bit rgb space after color conversion. each component is linearly interpolated using a triangle 2-tap filter. windowing and panning video images are clipped to a rectangular window by a pair of registers specifying the position and width. by programming the video start address and the video pitch, the video overlay logic also supports a panning window that can zoom into a portion of the source image. video composition with the color keying feature enabled, a program- mable key in the graphics pixel stream allows se- lection of either the video or the graphics output on a pixel by pixel basis. color keying allows any ar- bitrary portions of the video to overlay the graph- ics. with color keying disabled and video overlay turned on, the video output overlays the graphics in the video window. interlaced video the video overlay can display both non-interlaced and interlaced video. traditional video overlay hardware typically drops every other field of an interlaced video stream, resulting in a low frame rate. some solutions have attempted to overcome the this problem by de- interlacing the fields into a single frame. this however introduces motion artifacts. fast moving objects appearing in different positions in different fields, when deinterlaced, introduces visible artifacts which look like hair-like lines projecting out of the object.
128-bit 3d multimedia accelerator riva 128 38/77 figure 36. displaying 2 fields with 1:1 ratio the riva 128 video overlay handles interlaced vid- eo by displaying every field, at the original frame rate of the video (50hz for pal and 60hz for ntsc). the video scaling logic upscales , in the ver- tical direction ,t he luma components in each field and linearly interpolate s successive lines to pro- duce the missing lines of each field . this interpolat- ed scale is applied such that the full frame size of each field is stretched to the desired height. the video scaler offsets the bottom field image by half a source image line to ensure that both frames when played back align vertically. the vertical filtering results in a smooth high quality video playback. also by d isplaying both fields one af- ter another , any motion art i facts often found in dein- terlaced video output are removed , because the pix- els in each field are displayed in the order in which the original source was captured. line 10 interpolated line (line 10 & 12) line 12 line 11 line 13 interpolated line (line 11 & 13) frame 1 (top field) frame 2 (bottom field)
128-bit 3d multimedia accelerator riva 128 39/77 8 video port the riva 128 multimedia accelerator introduces a multi-function video port that has been designed to exploit the bus mastering functionality of the riva 128. the video port is compliant with a sim- plified itu-r-656 video format with control of at- tached video devices performed through the riva 128 serial interface. video port support includes: ? windows 95 directmpeg api acceleration by providing: - bus mastered compressed data transfer to attached dvd and mpeg-2 decoders - local interrupt and pixel stream handling - hardware buffer management of com- pressed data, decompressed video pixel data and decompressed audio streams ? supports popular video decoders including the philips saa7111a, saa7112, itt 3225, and samsung ks0127. the video port initiates transfers of video packets over the internal nv bus to either on or off screen surfaces as de- fined in the directdraw and directvideo apis. ? supports filtered down-scaling or decimation ? allows additional devices to be added figure 37. connections to multiple video modules 8.1 video interface port features ? single 8-bit bus multiplexing among four trans- fer types: video, vbi, host and compressed data ? synchronous 40mhz address/data multiplexed bus ? hardware-based round-robin scheduler with predictable performance for all transfer types ? supports multiple video modules and one rib- bon cable board on the same bus ? itu-r-656 master mode ? video port - simplified itu-r-656 video format -- sup- ports hsync, vsync, odd field and even field - vbi data output from video decoder is cap- tured as raw or sliced data pci/agp mpclk mpad[7:0] mpframe# mpdtack# mpstop# riva 128 video decoder media port controller (mpc) s video vmi 1.4 itu-r-656 dvd controller tv tuner sda scl
128-bit 3d multimedia accelerator riva 128 40/77 8.2 bi-directional media port polling commands using mpc the media port transfers data using a polling pro- tocol. the media port is enabled on the riva 128 by the host system software. the first cycle after being enabled is a poll cycle. the mpc asic must respond to every poll cycle with valid data during dtack active. if no transactions are need- ed, it responds with 00h. the media port will con- tinue to poll until a transaction is requested, or un- til there is a host cpu access to an external reg- ister. polling cycle media port initiates a polling cycle whenever there is no pending transaction. this gives the mpc asic a mechanism to initiate a transaction. the valid polling commands are listed in the poll- ing command table. the priority for the polling re- quests should be to give the display data fifo highest priority. cpu register write initiated by the host system software. cpu register read issue initiated by the host system software. the read differs from the write in the fact that it must be done in two separate transfers. the read issue is just the initiation of the read cycle. the media port transfers the address of the register to be read during this cycle. after completion of the read is- sue cycle the media port goes back to polling for the next transaction. when it receives a read data ready command, it will start the next cycle in the read. cpu register read receive initiated by the mpc asic when it has read data ready to be transferred to the media port. the mpc asic waits for the next polling cycle and re- turns a read data ready status. the media port will transfer the read data on the next read re- ceive cycle. the pci bus will be held off and retry until the register read is complete. video compressed data dma write initiated by the mpc asic with the appropriate polling command. the media port manages the video compressed data buffer in system memory. each request for data will return 32 bytes in a sin- gle burst. display data dma read initiated by the mpc asic with the polling com- mand. the mpc asic initiates this transfer when it wishes to transfer video data in itu-r-656 for- mat. table 9. media port transactions table 10. polling cycle commands a0 cycle transaction description 11xx0000 poll_cycle polling cycle 00xx---- cpuwrite cpu register write 01xx1111 cpuread_issue cpu register read issue 11xx1111 cpuread_receive cpu register read receive 01xx0001 vcd_dma_write video compressed data dma write 11xx1000 display_data_read display data dma read bit data description 0 000xxxx1 nv_pme_vmi_poll_uncd request dma read of display data 1 000xxx1x nv_pme_vmi_poll_vidcd request dma write of video compressed data 3 000x1xxx nv_pme_vmi_poll_int request for interrupt 4 0001xxxx nv_pme_vmi_poll_cpurdrec respond to read issue - read data ready 00000000 null no transactions requested
128-bit 3d multimedia accelerator riva 128 41/77 8.3 timing diagrams figure 38. poll cycle figure 39. poll cycle throttled by slave figure 40. cpu write cycle figure 41. cpu write cycle throttled by slave a0 d0 mpclk mpframe# mp_ad[7:0 ] mpdtack# a0 d0 mpclk mpframe# mp_ad[7:0 ] mpdtack# a0 d mpclk mpframe# mp_ad[7:0 ] mpdtack# a1 a0 d mpclk mpframe# mp_ad[7:0 ] mpdtack# a1
128-bit 3d multimedia accelerator riva 128 42/77 figure 42. cpu read issue cycle - cannot be throttled by slave figure 43. cpu read_receive cycle figure 44. cpu read_receive cycle - throttled by slave figure 45. cd write cycle - terminated by master a0 mpclk mpframe# mp_ad[7:0 ] a1/d a0 d0 mpclk mpframe# mp_ad[7:0 ] mpdtack# a0 d0 mpclk mpframe# mp_ad[7:0 ] mpdtack# a0 d0 d1 d2 d3 mpclk mpframe# mp_ad[7:0] mpdtack#
128-bit 3d multimedia accelerator riva 128 43/77 figure 46. cd write cycle - terminated by slave in middle of transfer figure 47. cd write cycle - terminated by slave on byte 31 figure 48. cd write cycle - terminated by slave on byte 32, no effect figure 49. ucd read cycle, terminated by master, throttled by slave a0 d0 d1 d2 xxx a0 d3 d4 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop# a0 d0 d30 xxx a0 d31 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop# a0 d0 d30 d31 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop# a0 xxx d1 d2 d3 d0 mpclk mpframe# mp_ad[7:0] mpdtack#
128-bit 3d multimedia accelerator riva 128 44/77 figure 50. ucd read cycle, terminated by slave, throttled by slave figure 51. ucd read cycle, slave termination after mpframe# deasserted, data taken figure 52. ucd read cycle, slave termination after mpframe# deasserted, data not taken figure 53. ucd read cycle, slave termination after mpframe# deasserted, data taken a0 xxx d1 d2 d0 mpclk mpdtack# mpstop# mpframe# mp_ad[7:0] a0 d1 d2 d3 d0 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop# a0 d1 d2 d3 d0 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop# a0 d1 d2 d0 mpclk mpframe# mp_ad[7:0] mpdtack# mpstop#
128-bit 3d multimedia accelerator riva 128 45/77 8.4 656 master mode table 11 shows the video port pin definition when the riva 128 is configured in itu-r-656 master mode. before entering this mode, riva 128 dis- ables all video port devices so that the bus is tri- stated. the riva 128 will then enable the video 656 master device through the serial bus. in this mode, the video device outputs the video data continuously at the pixclk rate. table 11. 656 master mode pin definition the 656 master mode assumes that vid[7:0] and pixclk can be tri-stated when the slave is inac- tive. if a slave cannot tri-state all its signals, an ex- ternal tri-state buffer is needed. video data capture video port pixel data is clocked into the port by the external pixel clock and then passed to the riva 128's video capture fifo. pixel data capture is controlled by the itu-r-656 codes embedded in the data stream; each active line beginning with sav (start active video) and ending with eav (end active video). in normal operation, when sav = x00, capture of video data begins, and when eav = xx1, capture of video data ends for that line. when vbi (vertical blanking interval) capture is active, these rules are modified. 656 master mode timing specification figure 54. 656 master mode timing diagram table 12. itu-r-656 master mode timing parameters note 1 vactive indicates that valid pixel data is being transmitted across the video port. table 13. yuv (ycbcr) byte ordering normal mode 656 master mode mpclk pixclk mpad[7:0] vid[7:0] mpframe# not used mpdtack# not used mpstop# not used symbol parameter min. max. unit notes t 3 vid[7:0] hold from pixclk high 0 ns t 4 vid[7:0] setup to pixclk high 5 ns t 5 pixclk cycle time 35 ns 1st byte 2nd byte 3rd byte 4th byte 5th (next dword) 6th byte 7th byte u[7:0] y0[7:0] v[7:0] y1[7:0] u[7:0] y0[7:0] v[7:0] cb[7:0] y0[7:0] cr[7:0] y1[7:0] cb[7:0] y0[7:0] cr[7:0] t 5 t 4 t 3 t 4 t 3 t 4 t 3 pixclk vid[7:0]
128-bit 3d multimedia accelerator riva 128 46/77 8.5 vbi handling in the video port riva 128 supports two basic modes for vbi data capture. vbi mode 1 is for use with the philips saa7111a digitizer, vbi mode 2 is for use with the samsung ks0127 digitizer. in vbi mode 1, the region to be captured as vbi data is set up in the saa7111a via the serial inter- face, and in the riva 128 under software control. the saa7111a responds by suppressing genera- tion of sav and eav codes for the lines selected, and sending raw sample data to the port. the riva 128 video port capture engine starts captur- ing vbi data at an eav code in the line last active and continues to capture data without a break until it detects the next sav code. vbi capture is then complete for that field. in vbi mode 2, the region to be captured as vbi data is set up in a similar manner. the ks0127 re- sponds by enabling vbi data collection only during the lines specified and framed by normal itu-r- 656 sav/eav codes. the riva 128 video port capture engine starts capturing data at an sav code controlled by the device driver, and contin- ues capturing data under control of sav/eav codes until a specific eav code identified by the device driver is sampled. vbi capture is then com- plete for that field. the number of bytes collected will vary depending on the setup of the ks0127. 8.6 scaling in the video port the riva 128 video port allows any arbitrary scale factor between 1 and 31. for best results the scale factors of 1, 2, 3, 4, 6, 8, 12, 16, and 24 are selected to avoid filtering losses. the video port decimates in the y-direction, dropping lines every few lines depending on the vertical scaling factor. the intention is to support filtered downscaling in the attached video decoder.
128-bit 3d multimedia accelerator riva 128 47/77 9 boot rom interface bios and initialization code for the riva 128 is accessed from a 32kbyte rom. the riva 128 memory bus interface signals fbd[15:0] and fbd[31:24] are used to address and access one of 64kbytes of data respectively. the unique decode to the rom device is provided by the romcs# chip select signal. figure 55. rom interface rom interface timing specification figure 56. rom interface timing diagram fbd[15:0] fbd[31:24] romcs# d[7:0] a[15:0] cs rom we riva 128 fbd[17] oe fbd[16] rom read t bas t brcs t bah t brca t brv t brh t bdbz t bds t bdh t bdz t bos address data fdb[15:0] romcs# oe# (fbd[16]) we# (fbd[17]) fdb[31:24] rom write t bas t brcs t bah t bwds t bwdh address data fdb[15:0] romcs# oe# (fbd[16]) we# (fbd[17]) fdb[31:24] t bws t bwl t boh
128-bit 3d multimedia accelerator riva 128 48/77 table 14. rom interface timing parameters note 1t mclk is the perio d of the internal memory clock. 2 this param eter is prog rammabl e in the range 0 - 3 mclk cycles 3 this param eter is prog rammabl e in the range 0 - 15 mclk cycles symbol parameter min. max. unit notes t brcs romcs# active pulse width 20t mclk -5 ns t brca romcs# precharge time t mclk -5 ns t brv read valid to romcs# active t mclk -5 ns t brh read hold from romcs# inactive t mclk -5 ns t bas address setup to romcs# active t mclk -5 ns t bah address hold from romcs# inactive t mclk -5 ns t bos oe# low from romcs# active ns 2 t boh oe# low to romcs# inactive ns 3 t bws we# low from romcs# active ns 2 t bwl we# low time ns 3 t bdbz data bus high-z to romcs# active t mclk -5 ns t bds data setup to romcs# inactive 10 ns t bdh data hold from romcs# inactive 0 ns t bdz data high-z from romcs# inactive t mclk -5 ns t bwdh write data hold from romcs# inactive 0.5t mclk -5 ns t bwds rom write data setup to romcs# active t mclk -5 ns
128-bit 3d multimedia accelerator riva 128 49/77 10 power-on reset configuration the riva 128 latches its configuration on the trail- ing edge of rst# and holds its system bus inter- face in a high impedance state until this time. to accomplish this, pull-up or pull-down resistors are connected to the fba[9:0] pins as appropriate. since there are no internal pull-up or pull-down re- sistors and the data bus should be floating during reset, a resistor value of 47k w should be suffi- cient. power-on reset fba[9:0] bit assignments [9] pci mode. this bit indicates whether the riva 128 initializes with pci 2.1 compliance 0 = riva 128 is pci 2.0 compliant (does not support delayed transactions) 1 = riva 128 is pci 2.1 compliant (supports 16 clock target latency requirement). [8:7] tv mode. these bits select the timing format when tv mode is enabled. 00 = reserved 01 = ntsc 10 = pal 11 = tv mode disabled [6] crystal frequency. this bit should match the frequency of the crystal or reference clock connect- ed to xtalout and xtalin . 0 = 13.500mhz (used where tv output may be enabled) 1 = 14.31818mhz [5] host interface 0 = pci 1 = agp (bit 0 must also be pulled high to indicate 66mhz) [4] ram width 0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state) 1 = 128-bit framebuffer data bus width [3:2] ram type 00 = reserved 01 = 8mbit sdram or sgram organized as 128k x 2 banks x 32-bit (normal sgram mode). 10 = reserved 11 = 8mbit sdram or sgram organized as 128k x 2 banks x 32-bit, framebuffer i/o pins remain tri-stated after reset. [1] sub-vendor. this bit indicates whether the pci subsystem vendor field is located in the system motherboard bios or adapter card vga bios. if the subsystem vendor field is located in the sys- tem bios it must be written by the system bios to the pci configuration space prior to running any pnp code. 0 = system bios (subsystem vendor id and subsystem id set to 0x0000) 1 = adapter card vga bios (subsystem vendor id and subsystem id read from rom bios at location 0x54 - 0x57) [0] bus speed. this bit indicates the value returned in the 66mhz bit in the pci configuration regis- ters (see page 64). 0 = riva 128 pci interface is 33mhz 1 = riva 128 is 66mhz capable 9876543210 pci mode tv mode crystal host interface ram width ram type sub- vendor bus speed
128-bit 3d multimedia accelerator riva 128 50/77 the following example configuration is shown in figure 57: ? subsystem vendor id initialized to 0 and writeable by system bios (see appendix a, page 70) ? 8mbit 128k x 2 bank x 32 sgram ? 128-bit framebuffer interface ? agp including 66mhz pci 2.1 compliant subset ? using 13.5000mhz crystal ? tv output mode is ntsc figure 57. example motherboard configuration 10k w 10k w riva 128 fba[1 ] fba[2] fba[3] sgram array vdd (3.3v) agp fba[4] fba[5] fba[8] fba[6] fba[7] fba[0 ] fba[9] fba[10]
128-bit 3d multimedia accelerator riva 128 51/77 11 display interface 11.1 palette-dac the palette-dac integrated into the riva 128 supports a traditional pixel pipeline with the follow- ing enhancements: ? support for 10:10:10, 8:8:8, 5:6:5 and 5:5:5 di- rect color pixel modes ? support for dynamic gamma correction on a pixel by pixel basis ? support for mixed indexed color and direct col- or pixels ? 256 x 24 lut for 8-bit indexed modes ? high quality video overlay - accepts interlaced video fields allowing a re- duction in memory buffering requirements while incorporating temporal averaging - line buffer for horizontal and vertical interpola- tion of video streams up to square pixel pal resolution - 3x2 multitap interpolating filter with image sharpening - color key in all color pixel modes - high quality yuv to rgb conversion with chrominance control. 11.2 pixel modes supported 8-bit indexed color in the 8-bit indexed color each 32-bit word contains four 8-bit indexed color pixels, each comprising bits b[7:0] as shown below. note 1 this 32-bit repre sentation can be extended to 64-bi t and 128- bit widths by duplicating the 32-b it word in little-endian format. 16-bit direct color modes (5:6:5 direct and 5:5:5 with and without gamma correction) in 5:5:5 color modes bit 15 of each pixel can be enabled to select whether pixel data bypasses the lut to feed the dacs directly, or indirectly, through the lut, to allow gamma correction to be applied. if not en- abled then the bypass mode will always be selected, and the lut powered down. the 16-bit modes in- clude a 5:6:5 format which always bypasses the lut. note 1 this 32-bit represent ation can be extended to 64-bi t and 128-bit widths by duplicating the 32-bi t word in little-endian for- mat. 32-bit direct color (8:8:8 with gamma correction or 10:10:10 direct) in 32-bit color mode bit 31 of each pixel selects whether pixel data bypasses the lut, to feed the dacs directly or indirectly, through the lut, to allow gamma correction to be applied. in the table below the red, green and blue bypass bits are shown individually as r[9:0], g[9:0], and b[9:0] because, in the bypass pixel formats (fbd[31:0]) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pixel 3 pixel 2 pixel 1 pixel 0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 5:6:5 mode pixel formats (fbd[31:0]) pixel 1 pixel 0 313029282726252423222120191817161514131211109876543210 0 0 red gamma green gamma blue gamma 0 red gamma green gamma blue gamma 0 1 red bypass green bypass blue bypass 1 red bypass green bypass blue bypass 1 red bypass green bypass blue bypass red bypass green bypass blue bypass
128-bit 3d multimedia accelerator riva 128 52/77 mode pixel format, the least significant bits of each color are located separately in the top byte of the pixel. this also permits an 8:8:8 mode without gamma with <1% error if desired. note this 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format. limitations on line lengths table 15. permitted line length multiples 11.3 hardware cursor the riva 128 supports a 32x32 15bpp full color hardware cursor as defined by microsoft win- dows. ? full color 5:5:5 format ? pixel complement ? transparency ? pixel inversion the cursor pattern is stored in a 2kbyte bitmap lo- cated in off-screen framestore. details of program- ming the hardware cursor are given in the riva 128 programming reference manual [2]. regis- ters control cursor enabling/disabling, location of cursor bitmap and cursor display coordinates. the cursor data and it's position should only be changed during frame flyback. the cursor should be disabled when not being used. cursor format the 5-bit rgb color components are expanded to 10 bits per color before combining with the graph- ics display data. the expanded 10-bit color is com- posed of the 5-bit cursor color replicated in the up- per and lower 5-bit fields. the cursor pixels are combined such that the cursor will overlay a video window if present. cursor pixel bit 15 (a) is the replace mode bit. when a=1, the cursor pixel replaces the normal display pixel. if a=0, the expanded 30 bits of the cursor color are xored with the display pixel to provide the complement of the background color. cursor pixels can be made transparent (normal display pixel is unmodified) by setting to a value of 0x0000. to invert the bits of the normal display pixel, the cursor pixel should be set to 0x7fff. use of pixel input pins (fbd[31:0]) pixel 0 313029282726252423222120191817161514131211109876543210 0 x x x x x x x red gamma green gamma blue gamma 1x r1 r0 g1 g0 b1 b0 r9 r8 r7 r6 r5 r4 r3 r2 g9 g8 g7 g6 g5 g4 g3 g2 b9 b8 b7 b6 b5 b4 b3 b2 bpp 8 16 32 number of pixels that the line length must be a multiple of 421 1514131211109876543210 a red green blue
128-bit 3d multimedia accelerator riva 128 53/77 11.4 serial interface the riva 128 serial interface supports connection to ddc1/2b, ddc2ab and ddc2b+ compliant monitors and to serial interface controlled video decoders and tuners. supported video decoder chips include philips saa7110, saa7111a, itt 3225 and samsung ks0127. for details of ad- dress locations and protocols applying to specific parts refer to the appropriate manufacturer's datasheet. the serial interface in riva 128 requires operation under software control to provide emulation of the interface standard. riva 128 can act as a master for communication with slave devices like those mentioned above. it also acts as a master when in- terfacing to a ddc1/2 compatible monitor. al- though it is not access.bus compatible, it can com- municate with a ddc2ab compatible monitor via the ddc2b+ protocol. (no other access.bus pe- ripherals can be attached although other serial de- vices may co-reside on the ddc bus). the riva 128 can clock stretch incoming messages in the event that the software handler is interrupted by another task.
128-bit 3d multimedia accelerator riva 128 54/77 11.5 analog interface figure 58. recommended circuit (crystal circuit is for designs not supporting tv out) table 16. table of parts for recommended circuit (figure 58) part number value description c1 22 m f tantalum capacitor c2 100nf surface mount capacitor c3, c4 22pf surface mount capacitor c5, c6 10nf surface mount capacitor r1 147 w 1% resistor r2-r4 75 w 1% resistor d1-d6 1n4148 protection diodes l1 1 m h inductor x1 13.50000mhz series resonant crystal (used where tv output may be required) 14.31818mhz series resonant crystal c2 monitor rset pllvdd vdd gnd vdd local pllvdd plane * * l1 75 w * these components should be placed as close to the riva 128 outputs as possible 75 w cable d1-d3 power supply c1 c5 r1 r2-r4 d4-d6 * xtalin c3 c4 x1 * comp red, green, blue xtalout riva 128 vref c6 dacvdd
128-bit 3d multimedia accelerator riva 128 55/77 11.6 tv output support reference clock options the riva 128 supports two synthesizer reference clock frequencies; 13.5mhz and 14.31818mhz. the reference clock frequency is determined by a crystal or reference clock connected to the xta- lin and xtalout pins. where tv-out is support- ed, xtalout should be driven by a 13.5mhz ref- erence clock derived from an external ntsc/pal clock source as illustrated in figure 59. the clock frequency should match the power-on configura- tion setting described in section 10, page 49. pal/ntsc tv interface the riva 128 supports tv output through an ex- ternal analog devices ad722 pal/ntsc rgb encoder chip as shown in figure 59. a microclock mk2715 ntsc/pal clock chip provides a com- mon source for synchronization of the pixel and subcarrier clocks. in tv output modes the riva 128 xtalout pin must be externally driven from the mk2715 reference clock output, with xtalin tied to gnd. the mk2715 requires a number of external com- ponents for proper operation. for crystal input a parallel resonant 13.5000mhz crystal is recom- mended, with a frequency tolerance of 50ppm or better. capacitors should be connected from x1 and x2 to gnd as shown in figure 59. alternative- ly a clock input (e.g. clockcan) can be connected to x1, leaving x2 disconnected. further details are given in the mk2715 datasheet [8]. figure 59. tv output implementation 75 w 75 w 75 w riva 128 r g b vidhsync ad722 tv rgb encoder rin gin bin hsync fin yout cout cvout 220 m f 220 m f 220 m f 75 w mk2715 ntsc/pal clock source 33 w 4xclk refout xtalout xtalin 33 w 330 w 220 w 5v 27pf 27pf 13.500 00mhz crystal x1/iclk x2
128-bit 3d multimedia accelerator riva 128 56/77 figure 60. interface to monitor or television monitor detection figure 60 shows the typical connection of a televi- sion or computer monitor to the riva 128s' dac outputs. the riva 128 expects only one output display device to be connected at a time and does not support simultaneous output to both the moni- tor and television. during system initialization, the bios detects if a monitor is connected by sensing the doubly-termi- nated 75 w load (net 37.5 w ). when no monitor is connected, only the local 75 w load is detected and the riva 128 switches to television output mode. the bios sets the crtc registers to generate the appropriate timing for the local television standard and the dacs are adjusted to compensate for the single 75 w load. monitor mode is always selected if a monitor is de- tected since it is assumed to be the output device of choice, having a higher display fidelity than tele- vision. timing generation televisions contain two phase-locked loops (plls). one pll locks the horizontal frequency and is used to synchronize horizontal and vertical flyback, and to keep the active video region stable and centered. the second pll locks the color subcarrier frequency (ntsc 3.5794545mhz or pal 4.43361875mhz). the color subcarrier is used as a phase reference to extract the color in- formation from the television signal. the riva 128 encodes horizontal and vertical tim- ing on a composite sync signal. using a 13.5000mhz reference clock, the riva 128 timing generator creates itu-r-601 ntsc and pal compliant horizontal timing with only ppm (parts per million) error. the riva 128 does not use the color subcarrier clock internally. the reference clock source can be located on the television up- grade module with the video encoder and tv out- put connectors, thus lowering the base system cost. flicker filter riva 128 provides an optional flicker filtering fea- ture for tv and interlaced displays. without flicker filtering, elements of an image present on either the odd or the even field, but not both, are seen to flicker or shimmer obtrusively. this is a problem especially with 1-pixel-wide hor- izontal lines often originating from computer gen- erated gui displays. flicker filtering causes a slight smearing of pixels in the vertical direction. this trades off image qual- ity versus flicker. the displayed pixel contains a proportion of the data for the pixel on that line, plus a smaller proportion of the data of the equivalent pixel on the line above and on the line below. overall, the proportions add up to 1 so that the brightness of the screen does not alter and the pix- el data does not get clipped. flicker filtering only takes place on pixel data from the framestore - the pattern written into the cursor already has flicker removed. no flicker removal is performed on video images. overscan and underscan the riva 128 supports overscan and underscan in the horizontal and vertical directions using hard- ware scaling. underscan allows 640x480 resolu- tion to fit onto ntsc displays and 800x600 resolu- tion to fit onto pal displays. scaling can be adjust- ed and controlled by software to suit specific tv requirements. the tv output image position is also software controllable. riva 128 r g b 75 75 75 monitor r g b y c y/c tv rgb encoder pal/ntsc television 75 75 75 75 75 75
128-bit 3d multimedia accelerator riva 128 57/77 12 in-circuit board testing the riva 128 has a number of features designed to support in-circuit board testing. these include: ? dedicated test mode input and dual-function test mode select pins selecting the following modes: - pin float - parametric nand tree - all outputs driven high - all outputs driven low ? checksum test ? test registers 12.1 test modes primary test control is provided by the dedicated testmode input pin. the riva 128 is in normal oper- ating mode when this pin is deasserted. when testmode is asserted, mp_ad[3:0] are reassigned as testctl[3:0] respectively. test modes are selected asynchronously through a combination of the pin states shown in table 17. table 17. test mode selection and descriptions 12.2 checksum test the riva 128 hardware checksum feature supports testing of the entire pixel datap ath at full video rates from the framebufferthrough to the dacinputs. each of the three rgb colors can be tested to provide a correlation between the intended and actual display. checksums are accumulated during active (un- blanked) display. note that the checksum mecha- nism does not check the dac outputs (i.e. what is physically being displayed on the monitor). for a given image (which can be a real application's image or a specially prepared test card), theoretical- ly derived checksum values can be calculated for a selected rgb color, which are then compared with the riva 128 hardwarechecksum value.alternative- ly the checksum value from a known good chip can be used as the reference. hardware checksum accumulation is not affected by the horizontal and vertical synchronization wave- forms or timings. any discrepancy between the cal- culated and riva128 hardwareaccumulated check- sum values therefore indicates a problem in the device or system being tested. details of program- ming the riva 128 checksum are given in the riva 128 programming reference manual [2]. test mode testctl[3:0] description 3210 parametric nand tree 1 0 1 0 a single parametric nand tree is provided to give a quiescent environ- ment in which to test vil and vih without requiring core activity. this capability is provided in the pads by chaining all i and i/o paths to- gether via two input nand gates. the chain begins with one input of the first nand gate tied to vdd while the other input is connected to the first device pin on the nand tree. the output of this gate then becomes the in- put of the next nand gate in the tree and so on until all pad input paths have been connected. the final nand gate output is connected to an out- put-only pin whose normal functionality is disabled in nand tree mode. the nand tree length is therefore equal to the number of i and i/o pins in the riva 128. output -only pins are not connected into the nand tree. pin float 1 1 0 0 all pin output drivers are tristated in this test mode so that pin leakage current (iil,iih,iozl,iozh) can be measured. outputs high 1 1 1 0 all pin output drivers drive a high output state in this test mode so that output high voltage (voh at ioh) can be measured. outputs low 1 1 1 1 all pin output drivers drive a low output state in this test mode so that out- put low voltage (vol at iol) can be measured.
128-bit 3d multimedia accelerator riva 128 58/77 13 electrical specifications 13.1 absolute maximum ratings 1 notes 1 stresses greater than those listed under `absolute maximum ratings' may cause permane nt damage to the device. this is a stress rating only and functional opera tion of the device at these or any other conditions above those indicated in the operat ional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe- riods may affect reliability. 2 for 3v tolerant pins vdd = 3.3v 0.3v, for 5v tolerant pins (pci, video port and serial interfaces) vdd = 5v 0.5v 13.2 operating conditions 13.3 dc specifications table 18. dc characteristics notes 1 includes high impedance output leakage for all bi-directional buffers with tri-state outputs 2 vdd = max, gnd vin vdd table 19. parameters applying to pci and agp interface pins symbol parameter min. max. units notes vdd/avdd dc supply voltage 3.6 v voltage on input and output pins gnd-1.0 vdd+0.5 v 2 ts storage temperature (ambient) -55 125 c ta temperature under bias 0 85 c analog output current (per output) 45 ma dc digital output current (per output) 25 ma symbol parameter min. typ. max. units notes tc case temperature 120 c symbol parameter min. typ. max. units notes vdd positive supply voltage 3.135 3.3 3.465 v iin input current (signal pins) 10 m a1,2 power dissipation 3.7 w symbol parameter min. typ. max. units notes cin input capacitance 5 10 pf 1 cout output load capacitance 5 50 pf 1 parameters for 5v signaling environment only: vih input logic 1 voltage 2.0 5.75 v vil input logic 0 voltage -0.5 0.8 v voh output logic 1 level 2.4 v vol output logic 0 level 0.55 v ioh output load current, logic 1 level -2 ma iol output load current, logic 0 level 3 or 6 ma 2 parameters for 3.3v and agp signaling environments only: vih input logic 1 voltage 0.475vdd vdd+0.5 v
128-bit 3d multimedia accelerator riva 128 59/77 note 1 tested but not guarant eed. 2 3ma for all signals except pciframe# , pcitrdy# , pciirdy# , pcidevsel# and pcistop# which have iol of 6ma. 13.4 electrical specifications table 20. parameters applying to all signal pins except pci/agp interfaces note 1 tested but not guarant eed. 2 for 3v tolerant pins vdd = 3.3v 0.3v, for 5v tolerant pins (video port and serial interfaces) vdd = 5v 0.5v 13.5 dac characteristics vil input logic 0 voltage -0.5 0.325vdd v voh output logic 1 level 0.9vdd v vol output logic 0 level 0.1vdd v ioh output load current, logic 1 level -0.5 ma iol output load current, logic 0 level 1.5 ma symbol parameter min. typ. max. units notes cin input capacitance 10 12 pf 1 cout output load capacitance 10 50 pf 1 vih input logic 1 voltage 2.0 vdd+0.5 v 2 vil input logic 0 voltage -0.5 0.8 v voh output logic 1 level 2.4 v vol output logic 0 level 0.4 v ioh output load current, logic 1 level -1 ma iol output load current, logic 0 level 1 ma parameter min. typ. max. units notes resolution 10 bits dac operating frequency 230 mhz white relative to black current 16.74 17.62 18.50 ma 2 dac to dac matching 1 2.5 % 2,4 integral linearity 0.5 1.5 lsb 8 2,3,8 differential linearity 0.25 1 lsb 8 2,3,8 dac output voltage 1.2 v 2 dac output impedance 20 k w risetime (black to white level) 1 3 ns 2,5,6 settling time (black to white) 5.9 ns 2,5,7 glitch energy 50 100 pvs 2,5 comparator trip voltage 280 335 420 mv comparator settling time 100 m s internal vref voltage 1.235 v internal vref voltage accuracy 3 5% symbol parameter min. typ. max. units notes
128-bit 3d multimedia accelerator riva 128 60/77 notes 1 blanking pede stals are not supported in tv output mode. 2 vref = 1.235v, rset = 147 w 3 lsb 8 = 1 lsb of 8-bit resolution dac 4 about the midpoint of the distribution of the three dacs 5 37.5oh m, 30pf load 6 10% to 90% 7 settling to within 2% of full scale deflection 8 monotonicity guaran teed 13.6 frequency synthesis characteristics note 1 a series resonant crystal should be connected to xtalin 2 the pixel clock can be prog rammed to within 0.5% of any target frequen cy 10 f pixclk 230mhz 3 the maximum pixel clock frequenc y when the riva 128 is displaying full motion video parameter min typ. max units notes xtalin crystal frequency range 4 15 mhz 1 internal vco frequency 128 256 mhz memory clock output frequency 100 mhz pixel clock output frequency 230 mhz 2 pixel clock output frequency (video displayed) 110 mhz 3 synthesizer lock time 500 m s
128-bit 3d multimedia accelerator riva 128 61/77 14 package dimension specification 14.1 300 pin ball grid array package figure 61. riva 128 300 plastic ball grid array package dimension reference table 21. riva 128 300 plastic ball grid array package dimension specification ref. millimeters inches typ. min. max. typ. min. max. a 2.125 2.595 0.083 0.102 a1 0.50 0.70 0.020 0.027 a2 1.625 1.895 0.064 0.074 b 0.60 0.90 0.024 0.035 d 27.00 26.82 27.18 1.063 1.055 1.070 d1 24.13 basic 0.951 basic d2 23.90 24.10 0.941 0.949 e 1.27 basic 0.050 basic e 27.00 26.82 27.18 1.063 1.055 1.070 e1 24.13 basic 0.951 basic e2 23.90 24.10 0.941 0.949 all dimensions in mm unless otherwise noted tolerances unless otherwise noted (mm) 0 10 >10 50 >50 200 >200 0.05 0.1 0.15 0.25 d2 e2 a1 c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y e d a b d1 e e1 e (4x) b solder ball (t yp) 0.25 0 a2 a 0.300 c a b 0.10 0 s c s ss c 0 .350 c 0.15 0 c 0.200 e e pin 1 indi cato r
128-bit 3d multimedia accelerator riva 128 62/77 15 references 1 riva 128 turnkey manufacturing package tmp, design guide , nvidia corp./sgs-thomson micro- electronics 2 riva 128 programming reference manual, nvidia corp./sgs-thomson microelectronics 3 accelerated graphics port interface specification, revision 1.0 , intel corporation , july 1996 4 pci local bus specification, revision 2.1 , pci special interest group, june 1995 5 recommendation 656 of the ccir, interfaces for digital component video signals in 525-line and 625- line television systems , ccir, 1990 6 display data channel (ddc ? ) standard, version 2.0, revision 0 , video electronics standards associ- ation, april 9th 1996 (video electronics standards association - http://www.vesa.org) 7 ad722 pal/ntsc tv encoder datasheet , analog devices inc., 1995 8 mk2715 ntsc/pal clock source datasheet , microclock inc., march 1997 16 ordering information device package part number riva 128 300 pin pbga stg3000x
128-bit 3d multimedia accelerator riva 128 63/77 appendix descriptions of register contents include an indication if register fields are readable (r) or writable ( w ) and the initial power-on or reset value of the field ( i ) . `-' indicates not readable / writable, x indicates an inde- terminate value, hence i = x indicates register or field not reset. a pci configuration registers this section describes the 256 byte pci configuration spaces as implemented by the riva 128. a single pci vga device is defined by the riva 128 which decodes and acknowledges the first 256 bytes of the configuration address space. the riva 128 does not respond (does not assert devsel# ) for functions 1-7. a.1 register descriptions for pci configuration space byte offsets 0x03 - 0x00 device identification register (0x03 - 0x02) vendor identification register (0x01 - 0x00) 0x03 0x02 0x01 0x00 313029282726252423222120191817161514131211109876543210 device_id_chip vendor_id bits function rwi 31:16 the device_id_chip bits contain the chip number allocated by the manu- facturer to identify the particular device. = 0x0018 r - 0x0018 bits function rwi 15:0 vendor_id bits allocated by the pci special interest group to uniquely identify the manufacturer of the device. nvidia/sgs-thomson vendor id = 0x12d2 (4818) r-x
128-bit 3d multimedia accelerator riva 128 64/77 byte offsets 0x07 - 0x04 device status register (0x07 - 0x06) command register (0x05 - 0x04) 0x07 0x06 0x05 0x04 313029282726252423222120191817161514131211109876543210 reserved serr_signalled received_master received_target reserved devsel_timing reserved 66mhz cap_list reserved reserved serr_enable reserved palette_snoop write_and_inva: reserved bus_master memory_space io_space bits function rwi 31 reserved r-0 30 serr_signalled is set whenever the riva 128 asserts serr#. r w 0 29 received_master indicates that a master device's transaction (except for special cycle) was terminated with a master-abort. this bit is clearable (=1). 0=no abort 1=master aborted rw0 28 received_target indicates that a master device's transaction was termi- nated with a target-abort. this bit is clearable (=1). 0=no abort 1=master received target aborted rw0 27 reserved r-0 26:25 the devsel_timing bits indicate the timing of devsel# . these bits indi- cate the slowest time that the riva 128 asserts devsel# for any bus com- mand except configuration read and configuration write. the riva 128 responds with medium devsel# for vga, memory and i/o accesses. for accesses to the 16mbyte memory ranges described by the bars, the chip responds with fast decode (no wait states). 00=fast 01=medium r-1 24:22 reserved r-0 21 66mhz indicates that the riva 128 is capable of 66mhz operation. this bit reflects the latched state of the 66mhz/33mhz strap option. r-1 20 cap_list indicates that there is a linked list of registers containing informa- tion about new capabilities not available within the original pci configuration structure. this bit indicates that the (byte) capability pointer register located at 0x34 points to the start of this linked list. r-1 19:16 reserved r-0 bits function rwi 15:9 reserved r-0
128-bit 3d multimedia accelerator riva 128 65/77 8 serr_enable is an enable bit for the serr# driver. 0=disables the serr# driver 1=enables the serr# driver rw0 7:6 reserved r-0 5 palette_snoop indicates that vga compatible devices should snoop their palette registers. 0=palette accesses treated like all other accesses 1=enables special palette snooping behavior rw0 4 write_and_inval is an enable bit for using the memory write and invali- date command. 1=the riva 128 as bus master may generate the command 0=the memory write command must be used instead of memory write and invalidate rw0 3 reserved r-0 2 bus_master indicates that the device can act as a master on the pci bus. 0=disables the riva 128 from generating pci accesses 1=allows the riva 128 to behave as a bus master rw0 1 memory_space indicates that the riva 128 will respond to memory space accesses . 0=device response disabled 1=enables response to memory space accesses. the device will decode and respond to the 16mbyte ranges as well as the default vga memory range when it is enabled. the vga decode range may change based upon the value in the vga graphics miscellaneous register gr06, bits[3:2] and other enable bits, see riva 128 programming reference manual [2]. rw0 0 io_space indicates that the device will respond to i/o space accesses . this bit enables i/o space accesses for the vga function as defined in the pci specific ation. these include 0x3b0 - 0x3bb, 0x3c0 - 0x3df and their aliases. rw0 bits function rwi
128-bit 3d multimedia accelerator riva 128 66/77 byte offsets 0x0b - 0x08 class code register (0x0b - 0x09) revision identification register (0x08) 0x0b 0x0a 0x09 0x08 313029282726252423222120191817161514131211109876543210 class_code revision_id bits function rwi 31:8 the class_code bits identify the generic function of the device and (in some cases) a specific register-level programming interface. the register is broken into three byte-size fields. the upper byte (at offset 0x0b) is a base class code which broadly classifies the type of function the device performs. the middle-byte (at offset 0x0a) is a sub-class code which identifies more specific ally the function of the device. the lower byte (at offset 0x09) identifies a specific register-level programming interface (if any) so that device indepen- dent software can interact with the device. the vga function responds as a vga compatible controller. 0x030000=vga compatible controller r-x bits function rwi 7:0 the revision_id bits specify a device specific revision identifier. the value is chosen by the vendor. this field should be viewed as a vendor defined extension to the device_id. 0x01=revision b r-x
128-bit 3d multimedia accelerator riva 128 67/77 byte offsets 0x0f - 0x0c 0x0f 0x0e 0x0d 0x0c 313029282726252423222120191817161514131211109876543210 reserved header_type reserved bits function rwi 31:24 reserved r-0 23:16 header_type identifies the device as single or multi-function. riva 128 responds as a single-function device. 0x00=single function device r - 0x00 16:00 reserved r-0
128-bit 3d multimedia accelerator riva 128 68/77 byte offsets 0x13 - 0x10 base memory address register (0x13 - 0x10) 0x13 0x12 0x11 0x10 313029282726252423222120191817161514131211109876543210 base_address base_reserved prefetchable address_type space_type bits function rwi 31:24 the base_address bits contain the most significant bits of the base address of the device. this indicates that the riva 128 requires a 16mbyte block of contiguous memory beginning on a 16mbyte boundary. this memory range contains memory-mapped registers and fifos and should not be set as part of a pentiumpro ? 's write combining range. rw0 23:4 the base_reserved bits form the least significant bits of the base address and are hardwired to 0. r-0 3 the prefetchable bit indicates that there are no side effects on reads, that the device returns all bytes on reads regardless of the byte enables, and that host bridges can merge processor writes into this range without causing errors. r-1 2:1 the address_type bits contain the type (width) of the base address. 0=32-bit r-0 0 the space_type bit indicates whether the register maps into memory or i/o space. 0=memory space r-0
128-bit 3d multimedia accelerator riva 128 69/77 byte offsets 0x17 - 0x14 base memory address register (0x17 - 0x14) byte offsets 0x2b - 0x18 base address registers (0x2b - 0x18) 0x17 0x16 0x15 0x14 313029282726252423222120191817161514131211109876543210 base_address base_reserved prefetchable address_type space_type bits function rwi 31:24 the base_address bits contain the most significant bits of the base address of the device. this indicates that the riva 128 requires a 16mbyte block of contiguous memory beginning on a 16mbyte boundary. this memory range contains linear frame buffer access and may be set as part of a pen- tiumpro ? 's write combining (wc) range. rw0 23:4 the base_reserved bits form the least significant bits of the base address and are hardwired to 0. r-0 3 the prefetchable bit indicates that there are no side effects on reads, that the device returns all bytes on reads regardless of the byte enables, and that host bridges can merge processor writes into this range without causing errors. r-1 2:1 the address_type bits contain the type (width) of the base address. 0=32-bit r-0 0 the space_type bit indicates whether the register maps into memory or i/o space. 0=memory space r-0 313029282726252423222120191817161514131211109876543210 0x00000000 bits function rwi 31:0 these bits are hardwired (read-only) to 0. r - 0
128-bit 3d multimedia accelerator riva 128 70/77 byte offsets 0x2f - 0x2c subsystem vendor id (0x2f - 0x2c) 0x2f 0x2e 0x2d 0x2c 313029282726252423222120191817161514131211109876543210 subsystem_id sub_vendor_id bits function rwi 31:16 subsystem_id is a unique code defined by the vendor to identify this prod- uct. r-0 15:0 sub_vendor_id bits allocated by the pci special interest group to uniquely identify the manufacturer of the sub-system. based on the strapping options read from rom during pci reset, this field may behave in one of two ways: 1 these bytes can be read from address locations 0x54 - 0x57 of the rom bios automatically during reset. this is useful for add-in card implementa- tions. 2 these bytes may be written from pci configuration space at locations 0x40 - 0x43. r-0
128-bit 3d multimedia accelerator riva 128 71/77 byte offsets 0x33 - 0x30 expansion rom base address register (0x33 - 0x30) 0x33 0x32 0x31 0x30 313029282726252423222120191817161514131211109876543210 rom_base_address rom_base_reserved reserved rom_decode bits function rwi 31:22 the rom_base_addr bits contain the base address of the expansion rom. the bits correspond to the upper bits of the expansion rom base address. this decode permits the pci boot manager to place the expansion rom on a 4mbyte boundary. riva 128 currently maps a 64kbyte bios into the bottom of this 4mbyte range. typically the first 32k of this rom contains the vga bios code as well as the pci bios expansion rom header and data structure. rwx 21:11 rom_base_reserved contain the lower bits of the base address of the expansion rom. these bits are hardwired to 0, forcing a 4mbyte boundary. r-0 10:1 reserved r-0 0 the rom_decode bit indicates whether or not the riva 128 accepts accesses to its expansion rom. when the bit is set, address decoding is enabled using the parameters in the other part of the base register. the memory_space bit (pci configuration register 0x04, page 64) has prece- dence over the rom_decode bit. riva 128 will respond to accesses to its expansion rom only if both the memory_space bit and the rom_decode bit are set to 1. 0=expansion rom address space is disabled 1=expansion rom address decoding is enabled rw0
128-bit 3d multimedia accelerator riva 128 72/77 byte offsets 0x37 - 0x34 capabilities pointer register (0x37 - 0x34) byte offsets 0x3b - 0x38 reserved (0x3b - 0x38) 0x37 0x36 0x35 0x34 313029282726252423222120191817161514131211109876543210 reserved cap_ptr bits function rwi 31:8 reserved r-0 7:0 this field contains a byte offset into this pci configuration space containing the first item in the capabilities list. this is a pointer to the extended capabili- ties list which returns 0x00000000 if the device is not strapped for agp (no extended capabilities ). r - 0x44 313029282726252423222120191817161514131211109876543210 0x00000000 bits function rwi 31:0 these bits are reserved and hardwired (read-only) to 0. r - 0
128-bit 3d multimedia accelerator riva 128 73/77 byte offset 0x3f - 0x3c max_lat register (0x3f ) min_gnt register (0x3e) interrupt pin register (0x3d) interrupt line register (0x3c) 0x3f 0x3e 0x3d 0x3c 313029282726252423222120191817161514131211109876543210 max_lat min_gnt interrupt_pin interrupt_line bits function rwi 31:24 the max_lat bits contain the maximum time the riva 128 requires to gain access to the pci bus. this read-only register is used to specify the riva 128's desired settings for latency timer values. the value specifies a period of time in units of 250ns. 1=250ns r-1 bits function rwi 23:16 the min_gnt bits contain the length of the burst period the riva 128 needs, assuming a clock rate of 33mhz. this read-only register is used to specify the riva 128's desired settings for latency timer values. the value specifies a period of time in units of 250ns. 3=750ns r-3 bits function rwi 15:8 the interrupt_pin bits contain the interrupt pin the device (or device func- tion) uses. a value of 1 corresponds to inta# . r-1 bits function rwi 7:0 the interrupt_line bits contain the interrupt routing information. post software will write the routing information into this register as it initializes and configures the system. the value in this field indicates which input of the sys- tem interrupt controller(s) the riva 128's interrupt pin is connected to. device drivers and operating systems can use this information to determine priority and vector information. interrupt_line is initialized to 0xff (no connec- tion) at reset. 0=interrupt line irq0 1=interrupt line irq1 0xf=interrupt line irq15 0xff=no interrupt line connection (reset value) r w 0xff
128-bit 3d multimedia accelerator riva 128 74/77 byte offsets 0x43 - 0x40 writeable subsystem vendor id (0x43 - 0x40) byte offsets 0x47 - 0x44 capabilities identifier register (offset = 0x47 - 0x44 = cap_ptr) 0x43 0x42 0x41 0x40 313029282726252423222120191817161514131211109876543210 subsystem_id sub_vendor_id bits function rwi 31:16 this subsystem_id field is aliased at 0x2f - 0x2e where it is read-only. it may be modified by system bios for systems which do not have a rom on the riva 128 data pins. this will ensure valid data before enumeration by the operating system. rw0 15:0 this sub_vendor_id field is aliased at 0x2d - 0x2c where it is read-only. it may be modified by system bios for systems which do not have a rom on the riva 128 data pins. this will ensure valid data before enumeration by the operating system. rw0 0x47 0x46 0x45 0x44 313029282726252423222120191817161514131211109876543210 reserved major minor next_ptr cap_id bits function rwi 31:24 reserved = 0x00 r - 0 23:20 this field indicates the major revision number of the agp specific ation that the riva 128 conforms to. = 0x01 r - 0x01 19:16 this field indicates the minor revision number of the agp specific ation that the riva 128 conforms to. = 0x00 r - 0x00 15:8 next_ptr contains the pointer to the next item in the capabilities list. this is the last entry in the capabilities list, hence it contains a null pointer = 0x00. r - 0x00 7:0 the cap_id field identifies the type of capability. agp = 0x02 r - 0x02
128-bit 3d multimedia accelerator riva 128 75/77 byte offsets 0x4b - 0x48 agp status register (0x4b - 0x48 = cap_ptr+4) 0x 0x 0x 0x 313029282726252423222120191817161514131211109876543210 rq reserved sba reserved rate bits function rwi 31:24 the rq field contains the maximum number of agp command requests this device can have outstanding. rq = 0x04 r - 0x04 23:10 reserved r-0 9 sba indicates whether the riva 128 supports sideband addressing. 0 = sideband addressing not supported r-0 8:2 reserved r-0 1:0 rate indicates the data transfer rate(s) supported by the riva 128. 01 = 66mhz 1x supported; 2x not supported r - 0x01
128-bit 3d multimedia accelerator riva 128 76/77 byte offsets 0x4f - 0x4c agp command register (0x4f - 0x4c = cap_ptr + 8) byte offset 0xff - 0x50 0x 0x 0x 0x 313029282726252423222120191817161514131211109876543210 rq_depth reserved sba_enable agp_enable reserved data_rate bits function rwi 31:24 this field is set to the minimum request depth of the target as reported in its rq field. rw- 23:10 reserved r-0 9 sba_enable enables sideband addressing when set. the riva 128 does not implement sideband addressing. r-0 8 agp_enable allows the riva 128 to act as an agp master and initiate agp operations. the target must be enabled before enabling the riva 128 0 = disabled 1 = agp operations enabled rw0 7:3 reserved r-0 2:0 the data_rate field must be set to 0x01 to indicate 66mhz/1x transfer mode. this value must also be set on the target before being enabled. r w 0x01 313029282726252423222120191817161514131211109876543210 reserved = 0x00000000
77/77 77 information furnished is believ ed to be accurate and reliable . however, sgs-thomson microelectronics assumes no responsibil ity f or the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result fr om its use. no licens e is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specificationsmen- tioned in this publication are subject to change without notice. this public ation supersedes and replaces all information previo usly supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems witho ut ex- press written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics inc. and nvidia corporation the sgs-thomson corporate logo is a registered trademark of sgs-thomson microelectronics. nvidia corporation, nvidia, and nv architecture are trademarks of nvidia corp. riva 128 is a trademark of sgs-thomson microelectronics and nvidia corp. microsoft, windows and the windows logo are registered trademarks of microsoft corporation all other products mentioned in this document are trademarks or registered trademarks of their respective owners. sgs-thomson microelectronics group of companies australia - brazil - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. nvidia corporation 1226 tiros way, sunnyvale, ca 94086, u.s.a sgs-thomson document number: 42 1687 01

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